Advancing High-Performance Compute with Customized Foundry Logic-Memory Integration

As High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads grow in scale and complexity, the industry is reaching a critical inflection point: system architectures must deliver far greater speed, bandwidth, and power efficiency to keep pace with rising data-processing and data-movement demands. This challenge—often referred to as the “memory wall”—reflects the need for closer, more advanced logic and memory solutions to unlock the full potential of next-generation compute systems.

Samsung Foundry is helping drive this shift by delivering advanced logic–memory integration solutions that combine high-bandwidth memory with its advanced process technologies, giving customers greater architectural flexibility and helping unlock the full potential of next-generation AI and HPC workloads.

Evolving requirements for AI and HPC systems

As compute workloads grow in scale and complexity, systems must continue advancing across four essential pillars: bandwidth, capacity, latency, and power. Each plays a critical role in overcoming data-movement bottlenecks and ensuring accelerators can sustain peak performance.

• Bandwidth: Data-intensive applications require dramatically higher throughput to keep pace with model growth and real-time processing.


• Capacity: Even with increasing memory density, expanding model sizes and datasets continue to push the need for greater system-level capacity.


• Latency: Real-time and high-performance applications depend on minimizing latency across the compute-memory pathway to maintain efficient processing cycles.


• Power: Energy-intensive AI workloads make system-wide power efficiency essential for sustained, scalable performance.

While memory technologies continue to evolve, the accelerating complexity of AI and HPC systems—and their data-centric behavior—imposes demands far beyond the capabilities of traditional architectures. This dynamic has intensified the need for more fundamental logic–memory co-design.

HBM: Advancing the future of high-performance compute

The industry is actively exploring new approaches to meet the demands of advanced AI and HPC workloads, and High-Bandwidth Memory (HBM) has become a cornerstone technology thanks to its exceptional bandwidth, power efficiency, and capacity. HBM is now widely adopted across leading AI inference and training accelerators, and the next stage of innovation lies in extending its capabilities through deeper logic-memory integration. To push performance even further, foundry logic base die integration with standard HBM is emerging as a powerful alternative—one that offers greater architectural flexibility, enhanced computational capability, and improved energy efficiency for next-generation systems.

Custom HBM chiplets: A next-generation solution

Custom HBM (cHBM) builds on the strengths of traditional HBM by leveraging a stacked architecture and through-silicon vias (TSVs) to deliver significantly higher bandwidth and lower latency—capabilities essential for high-performance data processing in AI and HPC systems. By manufacturing the base die on an advanced foundry process rather than a traditional memory process, cHBM enables the addition of custom logic functions directly beneath the memory stack. This approach unlocks new opportunities for performance optimization, power efficiency, and architectural innovation. Samsung Foundry is advancing this approach to help customers achieve greater system efficiency and architectural flexibility as logic and memory integration becomes increasingly important for modern compute.

cHBM chiplet architecture

cHBM introduces a set of architectural enhancements designed to improve data movement, efficiency, and scalability. By combining advanced logic processes, high-performance memory, and next-generation packaging technologies, cHBM enables more flexible and higher-performing solutions for AI and HPC applications.

• HBM controller integration: Integrating the HBM controller into the base die streamlines data pathways, reducing power consumption and latency while simplifying system design.


• High-performance die-to-die interfaces: A die-to-die (D2D) interface connects the SoC to the HBM chiplet, enabling faster data transfer, higher bandwidth and a reduced shoreline for more efficient system integration.


• Custom logic integration: Additional logic, such as accelerators or memory controllers, can be integrated into the logic base die, allowing architects to tailor performance for next-generation AI and HPC workloads.


• Advanced logic process for base die: By manufacturing the base die on an advanced process node – rather than a traditional memory node – designers gain higher performance, lower power, and reduced latency.


• Advanced packaging technologies: Cutting-edge packaging platforms allow customers to scale memory bandwidth both vertically (stack height) and horizontally (multi-chiplet clusters), enabling highly modular and high-bandwidth system architectures.

Benefits of foundry logic + HBM integration

Integrating advanced foundry logic with high-bandwidth memory delivers significant advantages across system performance, power efficiency, and overall design flexibility. By redefining the role of the HBM base die and enabling closer interaction between compute and memory, this approach enhances technical capabilities while providing greater scalability and long-term optimization potential for next-generation AI and HPC platforms.

Key benefits include:

• Increased bandwidth and capacity: The foundry logic base die offers an optimized shoreline and utilizes high-speed D2D interfaces, increasing bandwidth and supporting additional HBM stacks compared to traditional HBM PHY-based implementations.


• Reduced latency: Integrating the memory controller into the base die consolidates the entire HBM subsystem into a single die, minimizing external routing and reducing latency between compute and memory.


• Improved power efficiency: Transitioning the base die from an older memory process to an advanced logic process allows designers to take advantage of the inherent power-savings benefits of newer process technologies.


• Innovation and flexibility: Customized base die designs enable the integration of additional logic, such as accelerators, memory controllers, or CPUs, allowing for innovative solutions tailored to specific applications.

The path forward

As AI models expand toward the trillion-parameter scale, the industry faces a critical challenge: the “memory wall” is becoming a fundamental constraint on real-world HPC and AI performance. Chiplet-based architectures have already begun reshaping what is possible, and integrating a foundry logic base die with HBM marks the next major advancement in compute–memory co-design. By combining advanced logic process technology with integrated D2D interfaces, an embedded HBM controller, and customizable logic on the base die, this approach delivers substantial gains in bandwidth, capacity, performance, and efficiency.

Samsung is uniquely positioned to accelerate this transition through its aligned logic-process roadmap, deep memory expertise and advanced packaging platforms. This approach goes beyond incremental synergy—it reflects a deliberate, forward-looking strategy designed to enable the next generation of cHBM-based computing systems. With these integrated capabilities, Samsung is helping define the future of high-performance compute for the AI era.