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Integrated HPC solutions

for the AI
& 5G era

Samsung Foundry powers the most demanding HPC platforms with complete
end-to-end solutions including leading-edge process technology,

best-in-class IP,
advanced packaging and state-of-the-art design.

Samsung Foundry plays an instrumental role in
offering unmatched expertise to our customers,
designing performance-intensive solutions that are
the industry.

Foundry Services HPC solutions for

Unmatched performance expertise

Scaling efficiently

In an era of accelerated global transformations, we see a dramatic rise
in the deployment of AI and 5G technologies to
tackle increasingly complex workloads and analytics.

To enable these requirements, enterprise and hyper-scale cloud data centers, communication and networking platforms have become the foundation of our global industries. As such, they need to scale efficiently without compromising computing power, performance,
latency, bandwidth, and functionality.

Trusted foundry supplier

Samsung Foundry plays an instrumental role in providing unmatched expertise and innovation
to our customers designing performance and compute-intensive solutions that are reshaping this industry. Our commitment to technology innovation and manufacturing excellence are driven by our goal to become the most trusted foundry supplier in the rapidly evolving Mobile, AI, Networking, Performance and Storage segments. We are committed to providing
robust, reliable and innovative technologies
that integrate seamlessly to produce next-generation enhanced SOCs and Multi-Chip
Module platforms.

Meeting customer demands

Our high volume manufacturing capability and commitment to excellence puts us in a unique position to scale our production to meet our customer's demand at all stages of their product life cycle. Our regular investment in new production lines ensures adequate capacity on our advanced EUV nodes.

Your ultimate foundry partner for
performance-intensive applications

Samsung Foundry continues to power HPC, AI and advanced networking platforms through
technologies that deliver CPU and GPU engines, neural networks, storage and memory chips
as well as a broad range of interfaces and connectivity solutions.

  • FPGA Controllers
  • CPU Peripherals
  • SSD Controllers
  • Network Switch and Router
  • HBM
  • GPU
  • 5G Infrastructure

We’re ready for you.

Samsung Foundry's core technologies to fuel your next platform consist of:

  • Leading edge, cost-effective
    process node technologies

  • Advanced Packaging and

    Chiplet integrations

  • Flexible business engagement models for designs services & OSATs

  • Silicon-proven IPs built with

    industry-leading partners

  • Connectivity

  • Advanced storage and

    memory solutions

HPC Solutions

High-speed PHYs
  • Interface PHYs: PCIe, Ethernet, USB, multi-protocol SerDes

  • Chip to Chip: PCIe, CXL, CCIX, 56/112G SerDes (MR/LR)

  • Die to Die (Serial): 56/112G SerDes (XSR/VSR), proprietary

  • Die to Die (Parallel): HBM-like, HBI, BoW, proprietary

CUBE Technology
  • I-Cube: 2.5D Si-Interposer

  • R-Cube: 2.5D RDL Interposer

  • X-Cube: 3DIC

  • H-Cube: hybrid solution

Foundation IP
  • Standard cells

  • Memory compilers: SRAM/TCAM

  • Security: PUF & TRNG

Process technology
  • Advanced process technology

  • High-performance and low-power libraries with extensive DTCO

  • Optimized metal stacks

  • Performance Boost Kits

Process node technology

Always at the forefront of innovation, Samsung Foundry developed the first FinFET and EUV industry-leading process technologies that continue to fuel current and future platforms. Our technology experts can help you choose the right process node(s) for your target application(s) by offering you a broad and scalable portfolio of FinFET and EUV technologies. We continue to invest in next-generation advanced GAA technologies so that you will always have the performance, power, bandwidth, quality and reliability you need for first-time silicon success.

To guarantee higher performance, many Samsung Foundry processes have undergone additional optimizations at the transistor and standard cell level. They also include flexible metal stack options and higher-track libraries with performance boost kits. Additionally, these process nodes come with complete foundry services and supply chain support as you ramp up silicon.

Broad portfolio of
process technologies

  • Most cost
    14/11nm FinFET

    Millions of wafers

  • Best cost vs

    10/8nm FinFET

    Millions of wafers

  • Best
    7/5/4nm EUV

    Cutting edge high
    volume w/


  • Next level
    of PPA
    3nm GAA

    Next generation

Technology enablement for performance platforms Optimized transistor offering
  • High-performance transistors

  • Multi-Vt support including uLVT enablement

  • Overdrive support and ultra-low Vmin support for performance vs. power scaling

High-performance libraries including performance boost kits Optimized transistor offering
  • SRAM

  • Register Files

  • TCAMs

RC optimized metal stacks
high density MIM
design flow tuned to deliver high Peerformance
Technology Compute / Graphics Datacenter & Enterprise
N/W AI Storage
Ent D/C Training Interface Ent D/C
5nm, 4nm,
3nm GAA
5nm, 4nm,
3nm GAA
5nm, 4nm,
3nm GAA
8nm, 5nm 14/11nm
10/8nm, 5nm

Best-in-class IP for
intensive HPC

Samsung Foundry provides a broad portfolio of best in class IPs
optimized for your performance needs. Our portfolio consists of
dedicated as well as foundation IPs designed for your performance-
intensive applications. Furthermore, our foundation IP is optimized to best
your performance needs.

    • High performance
    • Low Latency
    • Optimized power/energy
    • Multi-protocol (MP) SERDES
    • D2D
    • PCIe
    • Ethernet
    • LPDDR
    • DDR
    • GDDR
    • HBM
    • Chip to Chip (C2C): CXL, CCIX
    • Die to Die (D2D): Serial & Parallel
IP 14nm/11nm 10/8nm 5nm 4nm
ADAS SerDes checked checked checked checked
D2D checked checked
PCIe checked checked checked checked
Ethernet checked checked checked checked
IVI LPDDR checked checked checked checked
DDR checked checked checked checked
GDDR checked checked checked checked
HBM checked checked checked checked
Analog IP checked checked checked checked
SRAM, TCAM checked checked checked checked

Design enablement

In a fast pace market, speed and productivity are key. Our customers measure our effectiveness through our ability to help them accelerate adoption, and ensure rapid integration while reducing design cycle times and increasing the productivity and success of their tape-outs and silicon. For this, we’ve established a design enablement platform to facilitate their designs and
optimize their cycle time.

Samsung Foundry design enablement platform encompasses:
  • A complete set of PDK files

  • Robust design flow methodologies that are node specific and
    downloadable for rapid design start

  • A full suite of libraries and IPs

  • A full suite of libraries and IPs

  • Robust design flow methodologies that are node specific and
    downloadable for rapid design starts

Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuring
that IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.

All these optimizations provide a robust and reliable design enablement platform which is essential, especially for early
adoptions of more recent technologies such as Samsung Foundry 5nm EUV,
3D IC and soon-to-be available GAA.

Design enablement files for EDA venders
DK/PDK(*) Datacenter & Enterprise
ANSYS Cadence Siemens EDA Synopsys Other
SPICE checked checked checked
P-Cell checked checked
DRC/Antenna checked checked checked
Dummy Insertion checked checked checked
LVS checked checked checked
RC Extraction checked checked checked
IR/EM checked checked checked
DFM checked checked checked
Design implementation ASIC steps
DK/PDK(*) Datacenter & Enterprise
ANSYS Cadence Siemens EDA Synopsys Other
RTL checked Arteris IP
Synthesis checked checked
DFT checked checked checked
PD/STA checked checked
PV/Sign-off checked checked checked
IR/EM checked checked checked

SAFE™ ecosystem

Ease of adoption, and rapid integration are essential in all high-performance designs. Samsung Foundry offers customers access to a comprehensive ecosystem of IP, design services, design enablement and implementation partners. Our SAFE™ program provides
a framework for these partnerships.

A broad ecosystem of services with our SAFE™ partners includes:
  • Best-in-class reference flows from major electronic design automation (EDA) vendors.

  • Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.

  • An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.

  • Predictive design-for-manufacturing solutions to address yield upstream in the design flow.

  • Advanced packaging and testing.

  • Design Service Partners

  • Cloud design support


SAFE™ Partners

We work very closely with every customer from the initial design concept to high-volume manufacturing, with transparency, and exceptionally flawless execution while delivering
the highest quality product.

Packaging for HPC and
networking chip designs

In this new era of high-performance computing and networking, designers are confronted with greater SOC
integration challenges to meet system performance requirements. As a result, new packaging technologies
and business models are being developed and deployed to overcome
these limitations while offering

customers a broader portfolio breadth for the optimal cost of ownership
(or price/performance ratios).

Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
  • Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)

  • Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor

Customers can choose one of our flexible business models to procure the package
solution that best meets their chip design:
  • I-Cube:
    2.5D Si-Interposer

  • R-Cube:
    2.5D RDL Interposer

  • X-Cube:

  • H-Cube:
    hybrid solution

I-Cube™ is Samsung's 2.5D Si Interposer technology that
horizontally connects logic devices with HBM (High Bandwidth Memory) modules.
  • Finer pitch
  • ISC, MIM in Si interposer
  • CoS: Low-cost with interim test
  • CoW: More HBM modules

The 300-mm TSV-bearing Silicon (Si) interposer wafer is
manufactured by Samsung Foundry. There are two
assembly processes depending on what format of Si
interposer is being used:
Chip on Substrate (CoS) or Chip
on Wafer (CoW). In CoS, the Si interposer chip comes from
a back-grinded and sawed Si interposer wafer. The chip is
assembled on the package substrate.
And then, the logic
devices and HBM modules are mounted on top of it. In
CoW, the logic devices and HBM modules are mounted on
the back-grinded Si interposer wafer by following the
wafer-level molding, grinding and sawing, and then the
molded Si interposer die with devices is mounted on the
package substrate. There is a major benefit with CoS:
interim testing.
Interim testing is for helping not to
mount any faulted interposer or logic chips before HBM
modules are mounted. There is a major benefit with CoW:
larger. A larger Si interposer can be
used for CoW. CoS
helps to develop low-cost 2.5D packages and CoW helps to
develop 2.5D packages with more HBM modules. Samsung
Foundry has successfully qualified I-Cube™ which
available in a wide range of interposer sizes, HBM
modules, and package sizes. Today, the 2.5D packages with
2x (1,600mm2) Si interposer integrating advanced logic
chip and up to four
HBM modules are fully qualified and
available for production. Larger 2.5D packages with larger
Si interposer integrating more than 4 HBM modules and
300nF/mm2 ISC™ (Integrated
Stack Capacitor) is in

R-Cube™ is Samsung’s low-cost 2.5D RDL Interposer technology that connects logic to logic and logic with HBM (High Bandwidth Memory) modules by high density RDL (Re Distribution Layer).
  • Low cost
  • TSV-less
  • Fast turn-around-time
  • Better signal and power integrity
  • Greater design flexibility

R-Cube™ is RDL first process known as “chip last”. Normally RDL layers are manufactured onto the carrier at the beginning of R-Cube™ process. By manufacturing the layers last, we achieve a faster Total Around Time (TAT) when compared to the chip first process. Additionally, by making the RDL later the known good ASIC and HBM could be mounted onto the RDL layer. There is a major benefit to an RDL interposer in that it is a low cost option as it a TSV-less solution. Also, RDL interposer shows much better SerDes Signal integrity (SI) due to extremely small signal via dimension and better Memory SI due to RDL metal thickness. Furthermore, the Low-loss dielectric materials used help achieve less dielectric losses. Also, RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.5D TSV-less RDL interposer technology with a line and space width of 2/2um and a large interposer (~1600mm2) integrating 4 HBM modules.

X-Cube™ is Samsung's 3DIC that stacks dies and wafers using Through Silicon Via (TSV) technology.
  • Higher density integration
  • Greater scaling in size
  • Lower latency
  • Higher bandwidth
  • Solder CoW: production proven
X-Cube™ leverages three key technologies: Chip on Wafer (CoW), Wafer on Wafer (WoW) and Through Silicon Via (TSV).
  • CoW stacks thin chips on top of a thinned wafer.
  • WoW stacks a wafer on a thinned wafer.
  • TSV vertically interconnects top and bottom chips and wafers.

The combination of these three technologies allows for higher density integration, greater scaling in size, improved power efficiency and lower latency. Samsung is in a leading position to offer highly reliable and competitive micro-bump 3DIC products such as High Bandwidth Memory (HBM) and CMOS Image Sensor (CIS) products. Samsung Foundry has implemented high bandwidth and low latency SRAM interface between 7LPP logic die and 7LPP SRAM die utilizing micro-bump CoW technology and logic TSV PDK for low power 3DIC applications such as AI inference. In addition our expertise and rapid high volume manufacturing allows us to secure high yield production at an early stage. We are ready for mass production based on micro-bump CoW and TSV for low power 3DIC applications. A bumpless hybrid Die to Wafer (D2W) technology is in development.

H-Cube™ consists of a fine-pitch substrate on top of a module
substrate and is for developing large and low-cost packages.
  • Cost-effective
  • Larger package size
  • Greater scaling in size
  • Greater integration flexibility

H-Cube™ consists of an interposer, a fine-pitch substrate and a module substrate. Samsung Foundry developed this solution to provide a cost-effective hybrid ( Multi Chip Module, 2.5D, 5.5D) solution in a large package size. The BGA ball pitch of a fine-pitch substrate is reduced from 1mm down to 0.4mm (or less ) to make it smaller and more cost effective: the price of a small size of the substrate is less than that of a big size. The module substrate placed underneath the fine-pitch substrate, has a large size (up to 200x200mm2) and is less costly than a fine-pitch substrate due to relaxed specifications. There are 3 major benefits on H-Cube™: cost-effectiveness, large package size and greater integration flexibility. The hybrid substrate is more cost effective than a single fine-pitch substrate for the same package size. The large package size allows for greater expansion as a function of the number of I/O or the additional components such as capacitors, PMIC, GDDR etc. Samsung Foundry is developing a large hybrid package size (85x85mm2) solution with a large silicon interposer that integrates 6 HBM modules.