The more technology evolves, the more elusive a one-size-fits all approach becomes. Great ideas should never be constrained by the temptations of a catch-all solution. At the same time, however, companies need to be freed up to pursue their ambitions, so they need a foundry business they can depend on for the insight and the flexibility to accommodate whatever needs might arise, even for the most unique innovations. In a future where trail-blazing technologies are pushing boundaries in every direction – from automotive to mobile and IoT to HPC and AI – is it possible to build a foundry that can unify everything in one place?
Samsung Foundry has been hard at work answering this question for years and, at October 2022’s SAFE Forum in San Jose, MJ Noh took to the stage to provide the latest on how the company is achieving just that. Responsible for the Foundry Design Service Team at Samsung Foundry headquarters in Korea, MJ’s talk covered how Samsung’s Advanced Design Platform is leveraging technologies like 2.5D and 3D solutions to provide customers with a turnkey service they know can accommodate the scale and specificity of tomorrow’s ideas.
Building a Total Design Solution Under One Roof
In previous forums, Samsung has focused on numerous branches of its Design Platform’s strong and wide-ranging capabilities in automobile, mobile, IoT and AI, including AEC-Q100 qualifications and ASIL standard readiness in automobile. HPC applications, meanwhile, have been growing particularly fast, and the foundry industry is looking to the dynamic modularity of chiplet architectures for answers. In all these areas, Samsung is remaining mindful of customer priorities when seeking a platform to work with: faster time to market through optimized production cycles and competitive Power, Performance and Area (PPA) capabilities, like DTCO (Design Technology Co-Optimization) and STCO (System Technology Co-Optimization). Finally, foundries need the ability to provide everything as part of a one-stop-shop of cutting edge design capabilities, with no third-party specialization required. Of course, providing all this is no simple matter.
“Traditional chip design methods are faced with limitations caused by high cost and integration factors,” said MJ. “Even with silicon scaling, the number of transistors has continued to increase, pushing the limit of the maximum reticle size available, while the demand to integrate chips with various functions like these continues to rise. This causes a serious cost issue in both design and manufacturing.”
As a result, MJ explained, scaling down the transistor size can never be enough to fulfill the growing complexity of applications, and this is where Samsung is taking the lead, thanks to constant progress in 2.5D and 3D chiplet solutions.