Mobile image sensors have already entered the era of 200 megapixels. Ultra-high resolution is no longer a special specification but a familiar benchmark for users, and it has become a common reference point in discussions about smartphone cameras.
Behind the achievement of packing 200 million pixels into a limited sensor area lies pixel miniaturization. In mobile devices, where the sensor form factor cannot be expanded indefinitely, integrating more pixels into the same area inevitably makes each individual pixel smaller. As pixels shrink, however, the amount of light each one can receive and process becomes constrained, and this constraint places a limit on extending HDR (High Dynamic Range)¹⁾ performance.
Meanwhile, the conditions under which users pick up their cameras are growing increasingly demanding. As scenes containing both very bright and very dark areas within a single frame become more common — backlighting at midday, intense illumination on night streets, indoor spaces with windows — HDR performance is no longer an optional feature in mobile image sensors.
The challenges facing image sensors do not end there. They must preserve the detail that high resolution delivers while simultaneously satisfying low-light image quality, frame rate²⁾, and power consumption. Increasing pixel count alone, in other words, is not enough. What matters just as much is how fully each small pixel can receive light and convert it into charge, and how efficiently the entire path operates as that signal travels from the pixel to the sensor output.
To address these challenges, Samsung Electronics developed DeepPix, a new pixel architecture. This article examines DeepPix across two parts. Part 1 offers an accessible look at the background behind DeepPix, how it differs from conventional pixels, and the design characteristics unique to it. Part 2 then takes a closer look at how each technology is implemented within the pixel, the principles behind its operation, and the resulting changes in system performance and image quality.
Since introducing the industry's first 200MP image sensor in 2021, Samsung Electronics has accumulated technologies for maintaining image quality while reducing pixel size from 0.7㎛ down to 0.5㎛. Integrating more pixels into a limited sensor area requires pixels to keep shrinking, yet as pixels get smaller, it becomes harder for each pixel to capture enough light and store enough charge. This is why the technology for making pixels smaller had to advance alongside the technology for preserving image quality in those smaller pixels.
ISOCELL's pixel technology has evolved in response to this challenge. Rather than simply integrating more pixels, it has advanced toward reducing interference between adjacent pixels and making more effective use of the light each pixel receives.
A representative example is DTI (Deep Trench Isolation)³⁾. DTI forms deep trenches between adjacent pixels to prevent light or charge from crossing over into neighboring pixels. While BDTI (Backside Deep Trench Isolation), which forms these trenches from the back side of the wafer, suppressed optical interference between pixels, FDTI (Full-depth Deep Trench Isolation), which isolates the entire pixel, further strengthened electrical isolation as well.
By making the boundaries between pixels more robust, FDTI also established the foundation for photodiodes (PD)⁴⁾ to actively utilize space in the vertical direction. Building on this, Samsung's FDTI pixels secured excellent Full Well Capacity (FWC)⁵⁾ and pixel isolation⁶⁾ characteristics.
DeepPix stands in the direct lineage of this ISOCELL pixel technology. Rather than replacing the existing isolation method with a different technology, it optimizes the pixel's storage, transfer, and reception structures together on the foundation FDTI established, drawing out even more of the potential inherent in conventional FDTI pixels. In effect, it extends the scope of ISOCELL's innovation from "more pixels" to "the entire process by which a single pixel handles light."
A pixel in an image sensor converts light entering through the lens into charge, then reads that charge out as an image signal. The amount of charge a pixel can hold before saturating is its FWC, a metric directly tied to the range of brightness information the pixel can process.
Light entering through the lens is converted into charge and stored in the PD. The accumulated charge then passes through the transfer gate⁷⁾ to the floating diffusion (FD)⁸⁾, where it is converted into a voltage signal. A pixel, in other words, reads light through three stages: storing charge, transferring it, and receiving it. The process becomes easier to grasp when compared to a structure that handles water. If the PD is the reservoir that converts light into charge and holds it, the transfer gate is the channel through which that stored charge moves, and the FD is the basin that receives the delivered charge and turns it into a voltage signal.
Expanding the capacity of any single stage is not enough on its own. Even if the PD stores more charge, the bottleneck simply shifts to the next stage when the transfer gate cannot move it all, or when the FD cannot accept the increased amount. A pixel's practical performance rises when the PD's storage capability, the charge transfer efficiency, and the FD's receiving capacity all support one another.
What happens when FWC falls short shows up immediately in the photograph. When light exceeds what a pixel can handle, any brightness difference beyond that point is no longer distinguished and collapses into a single value. A bright sky washing out into a white mass, or the lettering on a night sign disappearing into the glare, is precisely that result. When FWC has room to spare, by contrast, the brightness differences in bright areas of the same scene remain intact. The point at which a pixel saturates, in other words, sets the upper limit of its dynamic range⁹⁾. Holding more light therefore means raising that saturation point, widening the margin before the signal reaches its limit. Herein lies the reason FWC has become a key performance metric for ultra-high-resolution image sensors, where pixel miniaturization continues to advance.
One representative approach to extending HDR performance adds a separate high-capacity capacitor¹⁰⁾ inside the pixel. The concept is to catch the overflow — the charge a pixel cannot handle — in a dedicated storage space.
But this approach comes with clear trade-offs. Making room for a capacitor complicates the pixel structure and adds process steps. The more fundamental issue is signal quality. The separate space that catches the overflowing charge holds a lot, but it is not a clean space — it carries far more noise. The bright areas are captured, but the signal itself may come out less clean.
To make up for that noise, the sensor splits the reading into small-signal and large-signal passes and each, so do the circuits and readout¹¹⁾ operations needed to process each one multiply along with them. Circuit area and power consumption grow accordingly, and the time required to read and combine a single frame multiple times lengthens as well, placing a burden on the frame rate. Add the processes needed to incorporate the capacitor and its wiring structure, and manufacturing costs can rise too. In the end, extending HDR performance brings a corresponding increase in complexity — both in the pixel structure and across the sensor system as a whole.
DeepPix started from a different direction. Instead of adding a separate high-capacity storage space, it builds on the high FWC and excellent pixel isolation characteristics that FDTI pixels already possess. Rather than appending something new, it redesigns the structure so that the PD itself stores more charge and handles it efficiently within the pixel.
This approach reduces the need for additional storage elements and signal paths, easing the burden on noise, readout, power consumption, and process complexity alike. To raise HDR performance, DeepPix draws more efficiently on the potential already present in the pixel structure rather than adding more components to it.
For a pixel to turn light into an image signal, it must pass through three stages: storing charge, transferring it, and receiving it. What distinguishes DeepPix is that it did not simply enlarge one of these stages. It redesigned the pixel's entire structure so that all three could handle more charge without interruption.
Redesigning the existing pixel instead of adding new components
Some conventional HDR technologies add a separate high-capacity capacitor to store the charge a pixel cannot hold — much like installing an auxiliary tank beside the existing reservoir to catch the overflow. Adding new storage space, however, requires area within the pixel to place it and wiring to connect it, along with additional steps in the manufacturing process. A separate high-capacity capacitor is not only noisy — it also adds paths for reading out the stored signal, which complicates the circuitry. And reading and processing the signal multiple times puts pressure on both power consumption and frame time.
DeepPix takes a different route. Rather than adding a separate high-capacity storage element, it redesigns and repurposes the PD, FD, and wiring resources already present within the pixel. Instead of installing a new auxiliary tank, it makes more efficient use of the existing reservoir, channel, and receiving basin. This raises charge-handling capacity while helping to reduce the burden that additional components and process steps would bring.
Using the depth of silicon instead of widening the pixel
In mobile image sensors, there is little freedom to enlarge the sensor or the pixel area. The more pixels integrated into the same sensor area, the less space each individual pixel has to work with. This is why widening the PD laterally to increase storage capacity can only go so far.
DeepPix keeps the pixel's footprint — its area viewed from above — unchanged, while extending the PD's charge storage region deeper into the silicon. It works much like a vessel with the same opening but a deeper interior: it holds more water without taking up more room. This allows the PD to store more electrons without any increase in pixel size. The name DeepPix reflects this very approach: rather than widening the pixel, it draws on the depth within to increase the amount of light a single pixel of the same size can handle.
Widening the entire path a charge travels, not just the storage
Storing more charge in the PD does not by itself yield a larger image signal. Even with a larger storage space, some charge can remain behind in the PD if the passage out is not wide enough. Charge left behind this way cannot become part of the actual signal and can cause image lag — a trace carried over into the next frame.
Even when all the charge exits the PD, another bottleneck arises if the FD receiving it has too little capacity. It is much like releasing a large volume of water from a big reservoir: if the space catching it is small, the full capacity cannot be put to use. Real pixel performance improves only when the PD's storage capacity, the passage the charge travels through, and the FD's receiving capacity all grow together.
DeepPix enables the PD to store more charge while also improving the transfer path so that even charge held deep within can reach the FD. On top of that, it expanded the FD's capacity to fully accept the charge delivered to it. The result is a balanced signal path in which no bottleneck forms at any of the three stages — storage, transfer, or reception.
This design secures higher FWC and lower noise while also reducing the number of times an HDR signal must be read and easing the burden of additional process steps. Instead of continuously adding new components, it draws on the potential of the existing pixel structure to improve both pixel performance and the efficiency of the sensor system as a whole.
This design approach is realized through three core technologies: enhancing PD full-well capacity, achieving complete charge transfer with a Dual Vertical Transfer Gate (DVTG), and implementing high-capacity FD sharing.
ISOCELL's pixel technology has advanced by addressing two challenges at once: realizing more pixels and preserving image quality in smaller ones. Where BDTI and FDTI strengthened the boundaries between pixels, DeepPix builds on that foundation to extend the scope of innovation into the pixel's internal storage, transfer, and reception structures.
What DeepPix ultimately expanded, then, is not the physical size of the pixel but the capacity of a single small pixel to receive and process light. It does not stop at holding more charge; within one structure, it also moves that stored charge out in full and reliably converts it into an image signal.
Translating this concept into actual sensor performance, however, requires implementing each technology with precision inside the pixel. This involves increasing the PD’s storage capacity while establishing an internal structure that supports charge transfer, ensuring that electrons stored deep within the PD can be fully transferred, and providing the FD with sufficient capacity to accommodate the increased charge.
Part 2 examines how DeepPix's three core technologies were actually implemented. From high-energy, high-dose doping control to the charge transfer principles behind D-VTG and the capacity expansion achieved through FD sharing and metal resources, it takes a closer look at the design inside the pixel — along with the changes these technologies brought to the sensor system and the final image.
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