Samsung Electronics' Semiconductor Research Center presented the paper “First Demonstration of 3D Stacked FETs at Gate Pitch of 42 nm Featuring Triple Stacked Nanosheet Channels for Advanced Logic Applications” at the 2026 VLSI Symposium, held from June 14–18. This article aims to provide an accessible explanation of the significance of this research.
[Research highlight]
This work received an outstanding review score of 8.29 out of 10 during the 2026 VLSI Symposium paper evaluation process, ranking among the highest-scoring papers out of more than 1,000 submissions and earning recognition as a Best Paper. It was also selected as one of the 2026 VLSI Technical Highlights and featured in the symposium’s official Press Kit for media outreach. Additional information can be found in the official VLSI Symposium Press Kit↗.
Transistor architectures have continuously evolved—from planar transistors to FinFETs, and later to Gate-All-Around (GAA) structures—with each generation improving the ability to control electrical current more precisely. However, achieving further scaling in logic devices requires more than simply improving the control of individual transistors. Equally important is determining how n-type and p-type transistors can be arranged more efficiently.
One promising answer to this challenge is the 3D Stacked FET. In conventional designs, n-type and p-type transistors are placed side by side on a planar surface. In contrast, a 3D Stacked FET vertically stacks the two transistors. This approach enables more transistors to be integrated within the same footprint, offering a new pathway for advancing the scaling of next-generation logic devices.
In conventional logic circuits, n-type and p-type transistors are arranged side by side on the same plane. This architecture has been used successfully for decades and has played a critical role in enabling today’s high-performance semiconductor devices. However, as the demand for higher transistor density continues to increase, this planar arrangement faces growing limitations.
A city provides a useful analogy. When available land becomes scarce, urban planners initially reduce the spacing between buildings and use roads and open spaces more efficiently. Eventually, however, further horizontal expansion becomes impractical. At that point, the solution is to build upward. High-rise buildings create more usable space on the same piece of land by utilizing the vertical dimension.
Logic devices face a similar challenge. Arranging n-type and p-type transistors side by side can only achieve a certain level of density. By stacking them vertically, more transistors can be accommodated within the same chip area.
In other words, 3D Stacked FETs extend transistor placement from the two-dimensional plane into the vertical dimension.
The GAA architecture naturally supports this transition toward three-dimensional integration. Because GAA devices employ nanosheet channels that can be formed in multiple layers, they provide a technological foundation for stacking and controlling channels vertically. In this sense, 3D Stacked FETs are not a completely different technological direction from GAA; rather, they can be viewed as the next evolutionary step that extends the GAA platform into the third dimension.
At first glance, the concept of a 3D Stacked FET may appear straightforward. It seems as though the solution is simply to stack transistors on top of one another. In practice, however, implementing such a structure requires overcoming several significant technical challenges.
There are three major challenges:
First, sufficient current conduction paths must be secured.
Second, multiple channel layers must be formed uniformly and with high crystalline quality.
Third, the upper and lower transistors must be electrically isolated from one another.
This research presents technological solutions to each of these challenges.
3-1. Expanding the current path: Triple-stacked nanosheet channels
The channel is the pathway through which current flows in a transistor. If the channel width is insufficient, the transistor may not be able to deliver the required drive current when switched on, potentially limiting device performance.
A 3D Stacked FET offers significant advantages in reducing transistor footprint. However, while reducing area, it must also maintain sufficient current-carrying capability.
One of the key achievements of this work is the implementation of triple-stacked nanosheet channels in both the n-type and p-type transistors while vertically integrating them. By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint.
This demonstrates that 3D Stacked FETs can provide not only higher density but also sufficient current drive capability within a vertically integrated architecture.
3-2. Creating high-quality current paths: Advanced epitaxial growth for uniform silicon crystal layers
Channel width alone does not determine transistor performance. Even a wide current path can suffer from degraded electrical performance if it contains defects or structural irregularities.
In a multi-layer nanosheet architecture, channel quality becomes even more critical. Small variations in thickness, shape, or crystal quality between layers can lead to non-uniform current flow, ultimately affecting device performance and variability.
The situation is similar to a highway. Even if the road is wide, traffic cannot flow smoothly if the surface is uneven or if the lane widths vary significantly from one section to another.
The same principle applies to transistor channels. Uniform channel dimensions and high crystal quality are essential for stable current transport.
In GAA devices, nanosheet channels are formed by growing thin silicon-based crystal layers. In this work, the epitaxial growth process was precisely optimized to achieve highly uniform and defect-free nanosheet channels across multiple stacked layers.
This achievement goes beyond simply stacking channels. It demonstrates the ability to maintain consistent channel quality throughout the entire structure, providing a critical foundation for the performance and uniformity of future 3D Stacked FET technologies.
3-3. Separating the upper and lower transistors: Middle Dielectric Isolation (MDI)
Another key technology in 3D Stacked FETs is the ability to clearly separate the upper and lower transistors.
An apartment building provides a useful analogy. Although all residents share the same building, each floor is separated by ceilings and floors that reduce interference between occupants. Without this separation, noise and disturbances would easily travel between floors.
The same principle applies to 3D Stacked FETs. Because the upper and lower transistors are positioned extremely close to one another, a dedicated isolation structure is required to prevent unwanted electrical interaction. This role is fulfilled by the Middle Dielectric Isolation (MDI) layer.
The MDI is more than a simple insulating layer. It serves as a critical boundary that separates the upper and lower transistors and provides a structural reference for forming the gate stacks of each device.
N-type and p-type transistors require different electrical characteristics and therefore different gate materials. In conventional planar layouts, these devices can be separated laterally during fabrication. In a vertically stacked architecture, however, the two devices are positioned directly above and below one another, making precise control of the MDI location and thickness essential.
If the MDI layer is too thin or improperly positioned, electrical coupling between the upper and lower transistors may occur. Conversely, if the layer is too thick or non-uniform, it may complicate the formation of the gate structures required for each transistor.
For this reason, MDI can be considered just as important as the stacking technology itself. In a 3D Stacked FET, success depends not only on the ability to stack devices, but also on the ability to separate them with precision.
One particularly significant achievement of this work is the demonstration of a 3D Stacked FET with a gate pitch of just 42 nm. Gate pitch refers to the distance between neighboring gates, and reducing this distance enables higher transistor density.
As the gate pitch shrinks, however, fabrication becomes increasingly challenging. Channels, gates, source/drain regions, isolation layers, and contact structures must all be formed with exceptional precision within a very limited space.
The challenge is even greater for 3D Stacked FETs. In addition to conventional planar scaling, these devices require precise vertical stacking and isolation of transistors.
Demonstrating a 42 nm gate-pitch 3D Stacked FET therefore represents more than the introduction of a new transistor architecture. It provides evidence that 3D Stacked FETs are evolving into a practical technology pathway for next-generation logic devices.
Ultimately, the primary role of a transistor is to control electrical current. When turned off, leakage current must remain minimal. When turned on, sufficient current must flow to support circuit operation. Equally important, these characteristics must be consistently maintained across many devices on the same wafer.
In this study, the researchers demonstrated the current-control characteristics of both n-type and p-type transistors within a 42 nm gate-pitch 3D Stacked FET.
In addition, the team evaluated device uniformity by comparing the electrical characteristics of multiple devices across the wafer. Uniformity is a critical requirement for semiconductor manufacturing because practical chip production depends on millions—or even billions—of transistors exhibiting consistent behavior.
GAA represented a major innovation in transistor architecture, enabling superior electrostatic control of the channel. 3D Stacked FETs build upon that foundation by extending the GAA concept into the vertical dimension.
Logic technology is now moving beyond the challenge of simply making individual transistors smaller. Engineers must also determine how to arrange n-type and p-type transistors more efficiently, how to form multiple channel layers with high uniformity, and how to isolate vertically stacked devices with precision.
Through the demonstration of a 42 nm gate pitch, triple-stacked nanosheet channels, advanced epitaxial growth processes, Middle Dielectric Isolation (MDI), and validated electrical performance, this work highlights the technological potential of 3D Stacked FETs as a key enabler for future logic technologies.
The future of logic semiconductors is no longer confined to a two-dimensional plane. The stage for innovation is now expanding into the third dimension.
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