Samsung’s scale-down processes will continue to evolve, driving progress along its DRAM roadmap. EUV patterning will continue to advance thanks to High-NA, which will allow Samsung to enhance its patterning capabilities with smaller process steps. In addition, new metals with lower resistance will be introduced to shrink both word and bit lines.
Adopting these new materials can enable word- and bit-line resistance to be improved by 40% and 35%, respectively. This makes these key technologies for pushing the limits of cell size.
Dielectrics with higher-k and high aspect ratio contact-etching processes will also be crucial to ushering in the next phase of DRAM capacitors. Samsung has prepared for this as well and is fully equipped to atomically control the crystallinity of high-k dielectrics at the sub-nanometer scale. Using FinFET, Samsung can improve speed and power by 30% and 20%, respectively, for 0.9V operation.
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