Integrated HPC solutions

for the AI
& 5G era

The 300-mm TSV-bearing Silicon (Si) interposer wafer is
manufactured by Samsung Foundry. There are two
assembly processes depending on what format of Si
interposer is being used:
Chip on Substrate (CoS) or Chip
on Wafer (CoW). In CoS, the Si interposer chip comes from
a back-grinded and sawed Si interposer wafer. The chip is
assembled on the package substrate.
And then, the logic
devices and HBM modules are mounted on top of it. In
CoW, the logic devices and HBM modules are mounted on
the back-grinded Si interposer wafer by following the
wafer-level molding, grinding and sawing, and then the
molded Si interposer die with devices is mounted on the
package substrate. There is a major benefit with CoS:
interim testing.
Interim testing is for helping not to
mount any faulted interposer or logic chips before HBM
modules are mounted. There is a major benefit with CoW:
larger. A larger Si interposer can be
used for CoW. CoS
helps to develop low-cost 2.5D packages and CoW helps to
develop 2.5D packages with more HBM modules. Samsung
Foundry has successfully qualified I-Cube™ which
is
available in a wide range of interposer sizes, HBM
modules, and package sizes. Today, the 2.5D packages with
2x (1,600mm2) Si interposer integrating advanced logic
chip and up to four
HBM modules are fully qualified and
available for production. Larger 2.5D packages with larger
Si interposer integrating more than 4 HBM modules and
300nF/mm2 ISC™ (Integrated
Stack Capacitor) is in
development.

R-Cube™ is RDL first process known as “chip last”. Normally RDL layers are manufactured onto the carrier at the beginning of R-Cube™ process. By manufacturing the layers last, we achieve a faster Total Around Time (TAT) when compared to the chip first process. Additionally, by making the RDL later the known good ASIC and HBM could be mounted onto the RDL layer. There is a major benefit to an RDL interposer in that it is a low cost option as it a TSV-less solution. Also, RDL interposer shows much better SerDes Signal integrity (SI) due to extremely small signal via dimension and better Memory SI due to RDL metal thickness. Furthermore, the Low-loss dielectric materials used help achieve less dielectric losses. Also, RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.5D TSV-less RDL interposer technology with a line and space width of 2/2um and a large interposer (~1600mm2) integrating 4 HBM modules.

H-Cube™ consists of an interposer, a fine-pitch substrate and a module substrate. Samsung Foundry developed this solution to provide a cost-effective hybrid ( Multi Chip Module, 2.5D, 5.5D) solution in a large package size. The BGA ball pitch of a fine-pitch substrate is reduced from 1mm down to 0.4mm (or less ) to make it smaller and more cost effective: the price of a small size of the substrate is less than that of a big size. The module substrate placed underneath the fine-pitch substrate, has a large size (up to 200x200mm2) and is less costly than a fine-pitch substrate due to relaxed specifications. There are 3 major benefits on H-Cube™: cost-effectiveness, large package size and greater integration flexibility. The hybrid substrate is more cost effective than a single fine-pitch substrate for the same package size. The large package size allows for greater expansion as a function of the number of I/O or the additional components such as capacitors, PMIC, GDDR etc. Samsung Foundry is developing a large hybrid package size (85x85mm2) solution with a large silicon interposer that integrates 6 HBM modules.