As the performance of the Application Processor(AP) increases, so does the number of Input/Output(I/O) terminals. As part of this shift, the types of chips used in smartphones — as well as their shapes — vary, leading to a growing need for technologies that increase integration density per unit area by vertically stacking heterogeneous packages. This is where the Interposer Package on Package(I-PoP) comes in.
The I-PoP structure consists of an AP die mounted onto the Printed Circuit Board(PCB) substrate, and an interposer — which is stacked to connect the AP die to memory. The interposer is the most important component of the I-PoP because it connects the DRAM to the AP die. Through the application of an interposer, the shortened data signal path between the AP die and DRAM improves speed and performance, while the reduced mounting space enables additional area to be reallocated for further performance enhancements compared to an SCP*.
As the performance of the Application Processor(AP) increases, so does the number of Input/Output(I/O) terminals. As part of this shift, the types of chips used in smartphones — as well as their shapes — vary, leading to a growing need for technologies that increase integration density per unit area by vertically stacking heterogeneous packages. This is where the Interposer Package on Package(I-PoP) comes in.
The I-PoP structure consists of an AP die mounted onto the Printed Circuit Board(PCB) substrate, and an interposer — which is stacked to connect the AP die to memory. The interposer is the most important component of the I-PoP because it connects the DRAM to the AP die. Through the application of an interposer, the shortened data signal path between the AP die and DRAM improves speed and performance, while the reduced mounting space enables additional area to be reallocated for further performance enhancements compared to an SCP*.
As the performance of the Application Processor(AP) increases, so does the number of Input/Output(I/O) terminals. As part of this shift, the types of chips used in smartphones — as well as their shapes — vary, leading to a growing need for technologies that increase integration density per unit area by vertically stacking heterogeneous packages. This is where the Interposer Package on Package(I-PoP) comes in.
The I-PoP structure consists of an AP die mounted onto the Printed Circuit Board(PCB) substrate, and an interposer — which is stacked to connect the AP die to memory. The interposer is the most important component of the I-PoP because it connects the DRAM to the AP die. Through the application of an interposer, the shortened data signal path between the AP die and DRAM improves speed and performance, while the reduced mounting space enables additional area to be reallocated for further performance enhancements compared to an SCP*.
AP products continue to advance, enriching smartphone user’ experiences, and demand for thinner packages is increasing, while maintaining performance and enabling slimmer designs, enhanced hand-held comfort, and longer usage time. As a result, Fan-out Wafer Level Package(FoWLP) technology is being used to enable improved performance within a small form factor.
The basic structure of FoWLP consists of several elements. A Re-Distribution Layer(RDL) for electrical connection is formed under the AP die. The RDL, which is thinner than the interposer, is also formed on top of the AP die, creating an electrical connection between the AP die and memory. Copper posts are built between the upper and lower RDLs to electrically connect the top and bottom sides of the AP die.
This approach makes use of the RDL without a conventional PCB substrate, allowing the package to become even thinner — significantly contributing to reducing the thickness of the AP and mobile phones, as well as lowering the thermal resistance of the AP. The RDL enables fine-pitch routing that ensures Signal Integrity(SI) and enhances performance, making it one of the most important elements of FoWLP.
AP products continue to advance, enriching smartphone user’ experiences, and demand for thinner packages is increasing, while maintaining performance and enabling slimmer designs, enhanced hand-held comfort, and longer usage time. As a result, Fan-out Wafer Level Package(FoWLP) technology is being used to enable improved performance within a small form factor.
The basic structure of FoWLP consists of several elements. A Re-Distribution Layer(RDL) for electrical connection is formed under the AP die. The RDL, which is thinner than the interposer, is also formed on top of the AP die, creating an electrical connection between the AP die and memory. Copper posts are built between the upper and lower RDLs to electrically connect the top and bottom sides of the AP die.
This approach makes use of the RDL without a conventional PCB substrate, allowing the package to become even thinner — significantly contributing to reducing the thickness of the AP and mobile phones, as well as lowering the thermal resistance of the AP. The RDL enables fine-pitch routing that ensures Signal Integrity(SI) and enhances performance, making it one of the most important elements of FoWLP.
AP products continue to advance, enriching smartphone user’ experiences, and demand for thinner packages is increasing, while maintaining performance and enabling slimmer designs, enhanced hand-held comfort, and longer usage time. As a result, Fan-out Wafer Level Package(FoWLP) technology is being used to enable improved performance within a small form factor.
The basic structure of FoWLP consists of several elements. A Re-Distribution Layer(RDL) for electrical connection is formed under the AP die. The RDL, which is thinner than the interposer, is also formed on top of the AP die, creating an electrical connection between the AP die and memory. Copper posts are built between the upper and lower RDLs to electrically connect the top and bottom sides of the AP die.
This approach makes use of the RDL without a conventional PCB substrate, allowing the package to become even thinner — significantly contributing to reducing the thickness of the AP and mobile phones, as well as lowering the thermal resistance of the AP. The RDL enables fine-pitch routing that ensures Signal Integrity(SI) and enhances performance, making it one of the most important elements of FoWLP.
Mobile devices are increasingly being used in high-performance applications such as gaming and AI, which generate significantly more heat. This has further increased the need to lower thermal resistance so that mobile devices can maintain strong performance within their compact form factor.
To address these requirements, the upgraded FoWLP significantly improves the thermal resistance of the AP die by reducing the size of the DRAM that obstructs the heat dissipation path and attaching a HPB(Heat Path Block) to facilitate heat release. Additionally, High-k EMC* is applied to ensure that heat is efficiently transferred toward the HPB direction.
With these packaging innovations, Samsung’s mobile packaging technology enables efficient outward heat dissipation, resulting in up to a 16% reduction in thermal resistance compared to previous packages and delivering enhanced performance.
Together, these advances elevate the overall smartphone user experiences, enabling smoother and more consistent gaming, faster real-time interpretation and translation, improved LLM performance, faster object detection, enhanced photo-resolution upscaling, and more across everyday mobile use.
Mobile devices are increasingly being used in high-performance applications such as gaming and AI, which generate significantly more heat. This has further increased the need to lower thermal resistance so that mobile devices can maintain strong performance within their compact form factor.
To address these requirements, the upgraded FoWLP significantly improves the thermal resistance of the AP die by reducing the size of the DRAM that obstructs the heat dissipation path and attaching a HPB(Heat Path Block) to facilitate heat release. Additionally, High-k EMC* is applied to ensure that heat is efficiently transferred toward the HPB direction.
With these packaging innovations, Samsung’s mobile packaging technology enables efficient outward heat dissipation, resulting in up to a 16% reduction in thermal resistance compared to previous packages and delivering enhanced performance.
Together, these advances elevate the overall smartphone user experiences, enabling smoother and more consistent gaming, faster real-time interpretation and translation, improved LLM performance, faster object detection, enhanced photo-resolution upscaling, and more across everyday mobile use.
Mobile devices are increasingly being used in high-performance applications such as gaming and AI, which generate significantly more heat. This has further increased the need to lower thermal resistance so that mobile devices can maintain strong performance within their compact form factor.
To address these requirements, the upgraded FoWLP significantly improves the thermal resistance of the AP die by reducing the size of the DRAM that obstructs the heat dissipation path and attaching a HPB(Heat Path Block) to facilitate heat release. Additionally, High-k EMC* is applied to ensure that heat is efficiently transferred toward the HPB direction.
With these packaging innovations, Samsung’s mobile packaging technology enables efficient outward heat dissipation, resulting in up to a 16% reduction in thermal resistance compared to previous packages and delivering enhanced performance.
Together, these advances elevate the overall smartphone user experiences, enabling smoother and more consistent gaming, faster real-time interpretation and translation, improved LLM performance, faster object detection, enhanced photo-resolution upscaling, and more across everyday mobile use.
Global