[SAFE™ Forum 2023] Samsung Foundry Showcases Advanced Technology and Solutions

In San Jose, California, on June 28th, 2023, a large group of Samsung Foundry employees, partners, and customers from around the world gathered to attend SAFE™ Forum 2023. The forum covered the theme “Accelerate the Speed of Innovation” and Samsung’s newfound focus on ease of use. Specifically, the company shared details of its latest FinFET and next-generation Gate-All-Around (GAA) technologies during two of the tech sessions. Sangyun Kim, VP of Design Technology, presented on “Advanced Technology and Design Infrastructure.” In his presentation, he introduced the benefits of advanced technology and a new concept of design infrastructure for the adoption of new processes. Jongshin Shin, EVP of Samsung Foundry and Head of IP, also gave a presentation on “Advanced Design Solution for HPC and Automotive,” which detailed how Samsung Foundry can meet customers’ high-performance computing (HPC) design needs through its new advanced design solutions.

Samsung Foundry Establishes a Solid Foundation for 4nm and 2nm Processes Samsung Foundry has fully secured the long-term viability of the 4nm node. This has been achieved through the stabilization and maturation of the company’s process technology, as well as continuous refinement and optimization that have led to improved yields, reliability, and manufacturing robustness. In terms of IP preparation for SF4X, Samsung’s foundation IP and analog IP have demonstrated readiness for SAFE™ IP partners and the IP portfolio — with the newly-introduced DDR5 and D2D set to be completed within the foreseeable future. For GAA, however, Samsung Foundry will provide highly advanced SF2 technology that offers significant improvements in performance, power, and area over SF3 GAA. In addition, Samsung Foundry is accelerating the development of the SF2P process to meet the steadily growing demand for superfast computing. To reduce area even further, the Extreme High Density (xHD) library is enabled in SF2, lowering area in comparison to the HD library. Apart from its applications to GAA, SF2 technology has also advanced with Samsung Foundry achieving further PPA improvement. Area optimization has enjoyed a significant enhancement of the peripheral area of SRAM through the introduction of the xHD library. a The SF2 has been made to be completely compatible with SF3, which means Samsung Foundry customers can reuse SF3 designs and apply SF2 technology as they like. It also means the Hard IP from SF3 and SF2 Logic SRAM are compatible with each other and can be utilized again. Furthermore, high-speed IPs will soon be ready for mass production.

In addition to these developments, Kim discussed RISC-V¹ , an open standard instruction set architecture (ISA) that covers a wide range of applications from the internet of things (IoT) to HPC. In order to support customers’ need for this architecture, Samsung Foundry developed reference flows with SiFive and major EDA companies such as Cadence and Synopsys for SF4 and SF3.

Regarding ease of use, Kim said, “Samsung defines ‘Ease of Use’ as a new design paradigm. The technologies discussed here at SAFE are complex, and the ease-of-use approach is intended to result in solutions that customers can use more easily and efficiently.” As it concerns ease of use, scaled down technology has led to more complicated design rules, which then increases design size. This can be an obstacle for customers because it leads to advanced process technology requiring more resources and design time. However, Samsung Foundry is preparing various advanced design solutions such as those relating to design migration and a 3DIC design platform, which allow customers to implement their products more quickly and easily. Design resources and turnaround times (TATs) are two of the main obstacles in state-of-the-art design. Through solutions developed by Samsung Foundry, dual foundry sourcing customers with the same or minor register transfer level (RTL) changes can achieve resource/TAT reduction by extracting design-specific information from the reference design and migrating it to the Samsung Foundry process. This will also further assist them in achieving their PPA requirements. Samsung Foundry has introduced a 3DIC description language called “3DCODE” in the 3DIC reference flow in order to increase design flow optimization. Having engineers that work on OSAT, EDA, and chip implementation use one language makes it more convenient to perform database migration and have design spec-based discussions. 3DCODE also helps users make or change early analysis models more fluidly. To make it easier for customers to integrate the design flow into one tool, Samsung Foundry has also introduced a 3DIC platform. With it, customers can handle databases as well as conduct path connection checks and thermal/PI analysis with 3DCODE. And they can also design 3DICs in one environment using one 3DCODE script. Additionally, to configure all system components of 3DICs corresponding to various applications, Samsung Foundry will continue to strengthen the Multi-Die Integration (MDI) Alliance, ensuring that EDAs, OSATs, IP providers, and Foundry can collaborate on every product. Advanced Design Solutions for HPC and Automotive Applications In his presentation “Advanced Design Solution for HPC and Automotive,” EVP Jongshin Shin provided an estimate that the total foundry market in 2028 will be worth more than $200 billion². By that time, HPC/AI will surpass mobile to represent the largest share of the market. Furthermore, automotive represents the highest growth rate of any sector. Given their projected growth in the foundry market, both HPC and automotive are prime for technological advancement and are, therefore, a focal point of Samsung Foundry.

Shin said that customers in the HPC market require a design platform that’s more comprehensive than a traditional mobile platform. For example, HPC requires wider sets of high-speed interface IPs in advanced nodes, multi-dimensional design methodology, innovative memory solutions, and advanced packaging; and Samsung is the only company that provides all these solutions. The base of the design platform is IP, especially high-speed interface IPs. Due to increasing complexity, the design time for IPs sometimes takes longer than that of the system on a chip (SoC) itself. Thus, preparation of Silicon-proven HSI³ IP is a key factor for node selection. Samsung Foundry has been investing a lot in this high-speed IP readiness in advanced nodes. All HPC-HSI IPs — including UCIe and the latest GDDR7 — are either available or in the process of being developed, from SF5 to SF2. Memory performance, especially bandwidth and latency, is a key factor for HPC. Although high bandwidth memory (HBM) can provide impressive bandwidth, its latency is usually limited by the way it is integrated in the package. The traditional 2.5D approach requires a Si interposer channel of several millimeters. Therefore, it requires PHYs both on the SoC and HBM sides, and leads to inevitable latency and additional power consumption. In order to improve memory performance, Samsung Foundry is providing a new HBM access model using 3D-DRAM PHY. It has HBM core dies stacked directly on the SoC logic die without buffer-dies. The 3D-DRAM PHY replaces HBM PHYs for both SoCs and DRAM, while directly interacting with the HBM controller and DRAM core. With this new memory platform, the read and write latency can be reduced by 37% and 20%, respectively, which is a major advantage in HPC applications. Additionally, write power in DRAM operation is reduced by 40% and read power in DRAM is scaled down by 45%.

Finally, to place all the dies in the proper package, Samsung Foundry provides three advanced packaging solutions: I-CubeS, I-CubeE, and X-Cube. I-CubeS is a 2.5D package with Si interposers. Integration of six HBM2Es is already available, and eight HBM3s will be made available this year. I-CubeE is for embedded Si bridges with a 55-micron pitch bump supported for dense routing so it can be used for HBM and die-to-die (D2D) applications. It will be qualified⁴ with 3 logic dies and twelve HBM3s in the package. X-Cube, on the other hand, is for 3D integration. SF4 and SF5 with a 25um pitch micro bump will be available this year, and 4um-pitch hybrid copper bonding will be enabled in 2026. As for automotive applications, the increase of electric vehicles is accelerating the evolution of chips, not only in advanced driver-assistance system (ADAS) and in-vehicle infotainment (IVI) applications, but also in microcontrollers (MCUs), e-mirrors, cameras, and sensors. For all these functions, Samsung Foundry’s automotive infrastructure focus is reliability and safety. Foundry provides reliable auto-grade process-design kits (PDKs) and design kits (DKs), reflecting all automotive design rule checking (DRC) and models as well as SAFE™ IP with AEC-Q100 and ASIL. High performance is required for ADAS, IVI and MCU applications. In the case of MCUs, high-performance domain-based central and zonal architecture is becoming increasingly popular. Therefore, it is expected that FinFET technology will be utilized in next-generation MCUs. From the process perspective, these are the plans for performance capabilities:

• • SF2A and SF4A are targeting AG2
  • SF5A and 8LPU have already reached AG2 with sights set on AG1
  • 14LPU has achieved AG1
  • SF2A & SF4A are looking to attain AG2
  • SF5A & 8LPU have already qualified for AG2 with aims to reach AG1

Apart from these two sessions, additional keynote presentations included guest speakers from Ansys, Alphawave, and IBM, as well as welcoming remarks from Jongwook Kye, EVP and Head of Foundry Design Platform Development at Samsung Foundry. The welcoming remarks were covered in part one of this series. The forum also provided attendees various networking opportunities including the partner pavilion with 40 booths