In an era of accelerated global transformations, we see a dramatic rise in the deployment of AI and 5G technologies to tackle increasingly complex workloads and analytics.
To enable these requirements, enterprise and hyper-scale cloud data centers, communication and networking platforms have become the foundation of our global industries. As such, they need to scale efficiently without compromising computing power, performance, latency, bandwidth, and functionality.
In an era of accelerated global transformations, we see a dramatic rise in the deployment of AI and 5G technologies to tackle increasingly complex workloads and analytics.
To enable these requirements, enterprise and hyper-scale cloud data centers, communication and networking platforms have become the foundation of our global industries. As such, they need to scale efficiently without compromising computing power, performance, latency, bandwidth, and functionality.
In an era of accelerated global transformations, we see a dramatic rise in the deployment of AI and 5G technologies to tackle increasingly complex workloads and analytics.
To enable these requirements, enterprise and hyper-scale cloud data centers, communication and networking platforms have become the foundation of our global industries. As such, they need to scale efficiently without compromising computing power, performance, latency, bandwidth, and functionality.
Samsung Foundry plays an instrumental role in providing unmatched expertise and innovation to our customers designing performance and compute-intensive solutions that are reshaping this industry. Our commitment to technology innovation and manufacturing excellence are driven by our goal to become the most trusted foundry supplier in the rapidly evolving Mobile, AI, Networking, Performance and Storage segments. We are committed to providing robust, reliable and innovative technologies that integrate seamlessly to produce next-generation enhanced SOCs and Multi-Chip Module platforms.
Samsung Foundry plays an instrumental role in providing unmatched expertise and innovation to our customers designing performance and compute-intensive solutions that are reshaping this industry. Our commitment to technology innovation and manufacturing excellence are driven by our goal to become the most trusted foundry supplier in the rapidly evolving Mobile, AI, Networking, Performance and Storage segments. We are committed to providing robust, reliable and innovative technologies that integrate seamlessly to produce next-generation enhanced SOCs and Multi-Chip Module platforms.
Samsung Foundry plays an instrumental role in providing unmatched expertise and innovation to our customers designing performance and compute-intensive solutions that are reshaping this industry. Our commitment to technology innovation and manufacturing excellence are driven by our goal to become the most trusted foundry supplier in the rapidly evolving Mobile, AI, Networking, Performance and Storage segments. We are committed to providing robust, reliable and innovative technologies that integrate seamlessly to produce next-generation enhanced SOCs and Multi-Chip Module platforms.
Our high volume manufacturing capability and commitment to excellence puts us in a unique position to scale our production to meet our customer's demand at all stages of their product life cycle. Our regular investment in new production lines ensures adequate capacity on our advanced EUV nodes.
Our high volume manufacturing capability and commitment to excellence puts us in a unique position to scale our production to meet our customer's demand at all stages of their product life cycle. Our regular investment in new production lines ensures adequate capacity on our advanced EUV nodes.
Our high volume manufacturing capability and commitment to excellence puts us in a unique position to scale our production to meet our customer's demand at all stages of their product life cycle. Our regular investment in new production lines ensures adequate capacity on our advanced EUV nodes.
Samsung Foundry continues to power HPC, AI and advanced networking platforms through
technologies that deliver CPU and GPU engines, neural networks, storage and memory chips
as well as a broad range of interfaces and connectivity solutions.
Leading edge, cost-effective process node technologies
Leading edge, cost-effective process node technologies
Leading edge, cost-effective process node technologies
Advanced Packaging and Chiplet integrations
Advanced Packaging and Chiplet integrations
Advanced Packaging and Chiplet integrations
Flexible business engagement models for designs services & OSATs
Flexible business engagement models for designs services & OSATs
Flexible business engagement models for designs services & OSATs
Silicon-proven IPs built with industry-leading partners
Silicon-proven IPs built with industry-leading partners
Silicon-proven IPs built with industry-leading partners
Connectivity solutions
Connectivity solutions
Connectivity solutions
Advanced storage and memory solutions
Advanced storage and memory solutions
Advanced storage and memory solutions
To guarantee higher performance, many Samsung Foundry processes have undergone additional optimizations at the transistor and standard cell level. They also include flexible metal stack options and higher-track libraries with performance boost kits. Additionally, these process nodes come with complete foundry services and supply chain support as you ramp up silicon.
To guarantee higher performance, many Samsung Foundry processes have undergone additional optimizations at the transistor and standard cell level. They also include flexible metal stack options and higher-track libraries with performance boost kits. Additionally, these process nodes come with complete foundry services and supply chain support as you ramp up silicon.
To guarantee higher performance, many Samsung Foundry processes have undergone additional optimizations at the transistor and standard cell level. They also include flexible metal stack options and higher-track libraries with performance boost kits. Additionally, these process nodes come with complete foundry services and supply chain support as you ramp up silicon.
| Technology | Compute / Graphics | Datacenter & Enterprise | |||||
| N/W | AI | Storage | |||||
| Ent | D/C | Training | Interface | Ent | D/C | ||
| Process (recommended) |
5nm, 4nm, 3nm GAA |
14/11nm, 10/8nm |
5nm, 4nm, 3nm GAA |
5nm, 4nm, 3nm GAA |
8nm, 5nm | 14/11nm 10/8nm, 5nm |
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| Technology | Compute / Graphics | Datacenter & Enterprise | |||||
| N/W | AI | Storage | |||||
| Ent | D/C | Training | Interface | Ent | D/C | ||
| Process (recommended) |
5nm, 4nm, 3nm GAA |
14/11nm, 10/8nm |
5nm, 4nm, 3nm GAA |
5nm, 4nm, 3nm GAA |
8nm, 5nm | 14/11nm 10/8nm, 5nm |
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| IP | 14nm/1nm | 10/8nm | 5nm | 4nm |
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Samsung Foundry design enablement platform encompasses:
Samsung Foundry design enablement platform encompasses:
Samsung Foundry design enablement platform encompasses:
A complete set of PDK files
A complete set of PDK files
A complete set of PDK files
A full suite of libraries and IPs
A full suite of libraries and IPs
A full suite of libraries and IPs
Robust design flow methodologies that are node specific and downloadable for rapid design start
Robust design flow methodologies that are node specific and downloadable for rapid design start
Robust design flow methodologies that are node specific and downloadable for rapid design start
Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuring that IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.
All these optimizations provide a robust and reliable design enablement platform which is essential, especially for early adoptions of more recent technologies such as Samsung Foundry 5nm EUV, 3D IC and soon-to-be available GAA.
Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuring that IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.
All these optimizations provide a robust and reliable design enablement platform which is essential, especially for early adoptions of more recent technologies such as Samsung Foundry 5nm EUV, 3D IC and soon-to-be available GAA.
Samsung Foundry works closely with key design enablement and IP partners to optimize the tools and allow for higher design productivity. In addition, our SAFE-QEDA or EDA certification program allows for higher design and silicon success by ensuring that IP and customer designs meet Samsung Foundry process and packaging technology requirements. Furthermore, our design enablement partners have entered a new era of computational software where the convergence of System Level Design, Artificial Intelligence, and Electronic Design Automation offers enhancements for even greater design optimizations.
All these optimizations provide a robust and reliable design enablement platform which is essential, especially for early adoptions of more recent technologies such as Samsung Foundry 5nm EUV, 3D IC and soon-to-be available GAA.
| DK/PDK | Datacenter & Enterprise | ||||
| ANSYS | Cadence | Siemens EDA | Synopsys | Other | |
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A broad ecosystem of services with our SAFE™ partners includes:
A broad ecosystem of services with our SAFE™ partners includes:
A broad ecosystem of services with our SAFE™ partners includes:
Best-in-class reference flows from major electronic design automation (EDA) vendors.
Best-in-class reference flows from major electronic design automation (EDA) vendors.
Best-in-class reference flows from major electronic design automation (EDA) vendors.
Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.
Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.
Comprehensive libraries of standard cells, memory compilers, and I/O interfaces.
An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.
An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.
An extensive IP portfolio including mixed-signal, peripheral, multimedia cores, and interfaces.
Predictive design-for-manufacturing solutions to address yield upstream in the design flow.
Predictive design-for-manufacturing solutions to address yield upstream in the design flow.
Predictive design-for-manufacturing solutions to address yield upstream in the design flow.
Advanced packaging and testing.
Advanced packaging and testing.
Advanced packaging and testing.
Design Service Partners
Design Service Partners
Design Service Partners
Cloud design support
Cloud design support
Cloud design support
OSATS
OSATS
OSATS
Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution
that best meets their chip design:
Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)
Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)
Handoff Model: COT (Customer Owned Tooling), COPD (Customer Owned Physical Design)
Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor
Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor
Customers can choose from Samsung Foundry packaging offerings or those offered by our performance OSAT partners such as Amkor
Customers can choose one of our flexible business models to procure the package solution that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution that best meets their chip design:
Customers can choose one of our flexible business models to procure the package solution that best meets their chip design:
I-Cube S: 2.5D Si-Interposer
I-Cube S: 2.5D Si-Interposer
I-Cube S: 2.5D Si-Interposer
I-Cube E: 2.3D RDL-Interposer with Si-Bridge
I-Cube E: 2.3D RDL-Interposer with Si-Bridge
I-Cube E: 2.3D RDL-Interposer with Si-Bridge
X-Cube: 3DIC
X-Cube: 3DIC
X-Cube: 3DIC
The 300-mm TSV-bearing Silicon (Si) interposer wafer is manufactured by Samsung Foundry. There are two assembly processes depending on what format of Si interposer is being used: Chip on Substrate (CoS) or Chip on Wafer (CoW). In CoS, the Si interposer chip comes from a back-grinded and sawed Si interposer wafer. The chip is assembled on the package substrate. And then, the logic devices and HBM modules are mounted on top of it. In CoW, the logic devices and HBM modules are mounted on the back-grinded Si interposer wafer by following the wafer-level molding, grinding and sawing, and then the molded Si interposer die with devices is mounted on the package substrate. There is a major benefit with CoS: interim testing. Interim testing is for helping not to mount any faulted interposer or logic chips before HBM modules are mounted. There is a major benefit with CoW: larger. A larger Si interposer can be used for CoW. CoS helps to develop low-cost 2.5D packages and CoW helps to develop 2.5D packages with more HBM modules. Samsung Foundry has successfully qualified I-Cube S which is available in a wide range of interposer sizes, HBM modules, and package sizes. Today, the 2.5D packages with 2x (1,600mm2) Si interposer integrating advanced logic chip and up to four HBM modules are fully qualified and available for production. Larger 2.5D packages with larger Si interposer integrating more than 4 HBM modules and 2000nF/mm2 ISC™ (Integrated Stack Capacitor) is in development.
The 300-mm TSV-bearing Silicon (Si) interposer wafer is manufactured by Samsung Foundry. There are two assembly processes depending on what format of Si interposer is being used: Chip on Substrate (CoS) or Chip on Wafer (CoW). In CoS, the Si interposer chip comes from a back-grinded and sawed Si interposer wafer. The chip is assembled on the package substrate. And then, the logic devices and HBM modules are mounted on top of it. In CoW, the logic devices and HBM modules are mounted on the back-grinded Si interposer wafer by following the wafer-level molding, grinding and sawing, and then the molded Si interposer die with devices is mounted on the package substrate. There is a major benefit with CoS: interim testing. Interim testing is for helping not to mount any faulted interposer or logic chips before HBM modules are mounted. There is a major benefit with CoW: larger. A larger Si interposer can be used for CoW. CoS helps to develop low-cost 2.5D packages and CoW helps to develop 2.5D packages with more HBM modules. Samsung Foundry has successfully qualified I-Cube S which is available in a wide range of interposer sizes, HBM modules, and package sizes. Today, the 2.5D packages with 2x (1,600mm2) Si interposer integrating advanced logic chip and up to four HBM modules are fully qualified and available for production. Larger 2.5D packages with larger Si interposer integrating more than 4 HBM modules and 2000nF/mm2 ISC™ (Integrated Stack Capacitor) is in development.
The 300-mm TSV-bearing Silicon (Si) interposer wafer is manufactured by Samsung Foundry. There are two assembly processes depending on what format of Si interposer is being used: Chip on Substrate (CoS) or Chip on Wafer (CoW). In CoS, the Si interposer chip comes from a back-grinded and sawed Si interposer wafer. The chip is assembled on the package substrate. And then, the logic devices and HBM modules are mounted on top of it. In CoW, the logic devices and HBM modules are mounted on the back-grinded Si interposer wafer by following the wafer-level molding, grinding and sawing, and then the molded Si interposer die with devices is mounted on the package substrate. There is a major benefit with CoS: interim testing. Interim testing is for helping not to mount any faulted interposer or logic chips before HBM modules are mounted. There is a major benefit with CoW: larger. A larger Si interposer can be used for CoW. CoS helps to develop low-cost 2.5D packages and CoW helps to develop 2.5D packages with more HBM modules. Samsung Foundry has successfully qualified I-Cube S which is available in a wide range of interposer sizes, HBM modules, and package sizes. Today, the 2.5D packages with 2x (1,600mm2) Si interposer integrating advanced logic chip and up to four HBM modules are fully qualified and available for production. Larger 2.5D packages with larger Si interposer integrating more than 4 HBM modules and 2000nF/mm2 ISC™ (Integrated Stack Capacitor) is in development.
I-Cube E gets more cost-effective over a silicon interposer as the size of the interposer becomes much larger but still be able to take the advantage of small L/S from silicon bridges embedded in the RDL interposer based on PLP technology and used as interfaces between silicon dies. Superior warpage control and power integrity in I-Cube E enables the next generation chiplet architectures possible for many years to come.
There is a major benefit to an RDL interposer in that it is a low cost option as it a Si-Bridge solution. Also, RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.3D RDL interposer technology with a line and space width of 2/2um and a large interposer (~1600mm2) integrating 4 HBM modules.
I-Cube E gets more cost-effective over a silicon interposer as the size of the interposer becomes much larger but still be able to take the advantage of small L/S from silicon bridges embedded in the RDL interposer based on PLP technology and used as interfaces between silicon dies. Superior warpage control and power integrity in I-Cube E enables the next generation chiplet architectures possible for many years to come.
There is a major benefit to an RDL interposer in that it is a low cost option as it a Si-Bridge solution. Also, RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.3D RDL interposer technology with a line and space width of 2/2um and a large interposer (~1600mm2) integrating 4 HBM modules.
I-Cube E gets more cost-effective over a silicon interposer as the size of the interposer becomes much larger but still be able to take the advantage of small L/S from silicon bridges embedded in the RDL interposer based on PLP technology and used as interfaces between silicon dies. Superior warpage control and power integrity in I-Cube E enables the next generation chiplet architectures possible for many years to come.
There is a major benefit to an RDL interposer in that it is a low cost option as it a Si-Bridge solution. Also, RDL interposer provides more design flexibility for less routing interference with fine line width and line spacing. Samsung Foundry is developing a 2.3D RDL interposer technology with a line and space width of 2/2um and a large interposer (~1600mm2) integrating 4 HBM modules.
X-Cube leverages three key technologies: Chip on Wafer (CoW), Wafer on Wafer (WoW) and Through Silicon Via (TSV).
CoW stacks thin chips on top of a thinned wafer.
WoW stacks a wafer on a thinned wafer.
TSV vertically interconnects top and bottom chips and wafers.
The combination of these three technologies allows for higher density integration, greater scaling in size, improved power efficiency and lower latency. Samsung is in a leading position to offer highly reliable and competitive micro-bump 3DIC products such as High Bandwidth Memory (HBM) and CMOS Image Sensor (CIS) products.. In addition our expertise and rapid high volume manufacturing allows us to secure high yield production at an early stage. We are ready for mass production based on micro-bump CoW and TSV for low power 3DIC applications. A bumpless hybrid Die to Wafer (D2W) technology is in development.
X-Cube leverages three key technologies: Chip on Wafer (CoW), Wafer on Wafer (WoW) and Through Silicon Via (TSV).
CoW stacks thin chips on top of a thinned wafer.
WoW stacks a wafer on a thinned wafer.
TSV vertically interconnects top and bottom chips and wafers.
The combination of these three technologies allows for higher density integration, greater scaling in size, improved power efficiency and lower latency. Samsung is in a leading position to offer highly reliable and competitive micro-bump 3DIC products such as High Bandwidth Memory (HBM) and CMOS Image Sensor (CIS) products.. In addition our expertise and rapid high volume manufacturing allows us to secure high yield production at an early stage. We are ready for mass production based on micro-bump CoW and TSV for low power 3DIC applications. A bumpless hybrid Die to Wafer (D2W) technology is in development.
X-Cube leverages three key technologies: Chip on Wafer (CoW), Wafer on Wafer (WoW) and Through Silicon Via (TSV).
CoW stacks thin chips on top of a thinned wafer.
WoW stacks a wafer on a thinned wafer.
TSV vertically interconnects top and bottom chips and wafers.
The combination of these three technologies allows for higher density integration, greater scaling in size, improved power efficiency and lower latency. Samsung is in a leading position to offer highly reliable and competitive micro-bump 3DIC products such as High Bandwidth Memory (HBM) and CMOS Image Sensor (CIS) products.. In addition our expertise and rapid high volume manufacturing allows us to secure high yield production at an early stage. We are ready for mass production based on micro-bump CoW and TSV for low power 3DIC applications. A bumpless hybrid Die to Wafer (D2W) technology is in development.
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