Samsung Opens the Gate to Transistor Performance, Power, and Area Improvements with MBCFET

In the past two years, COVID’s impacts were felt across the globe and in several industries, interrupting productions or even halting them completely in some cases. Despite unforeseen challenges, however, Samsung Foundry was able to continue its development and take lead, bringing new semiconductor solutions that meet the ever-growing industry needs by improving performances while reducing power consumption and area use. The keys to Samsung’s success amidst global challenges are two folds: an evolution of Gate-all-around (GAA) technology and the optimization of designs with the help of industry partners. Building on GAA with MBCFET™

When Samsung first led the industry by transitioning from planar to FinFET transistors, in many ways, it set a new standard for semiconductor processes. Utilizing the FinFET architecture, Samsung was able to overcome short channel effects that had put a limit to planar transistors. GAA followed thereafter, allowing for improved voltage scaling with the use of nanowires. Nanowire-based transistor technology improved drive current with raised channels but it came at the cost of low leakage current – ultimately limiting its advantage. Whereas nanowires require a larger number of stacks to provide enough current, each nanosheet-based MBCFET™ drives larger current with larger channel width that requires fewer number of stacks overcoming the limits of GAA. With the introduction of multi-bridge-channel FET (MBCFET™) utilizing nanosheets, Samsung again took a leap forward in transistor architecture making it possible to deliver flexible designs, low voltage operations and excellent performance in a smaller footprint. This allows for low-voltage on-and-off control and high-efficiency operation. The result are cost-effective, high-performance transistors using smaller footprints that are easily scalable. More important than improvement for improvement’s sake, MBCFET™ designs are what’s needed for use in advanced sectors like automotive, AI/ML and large-scale databases where high-performance, low power consumption and small area use are essential. Maximizing Transistor Efficiency with Design-Technology Co-Optimization

Though the solutions for overcoming nanowires-based GAA architecture limits may seem straightforward, it required finding the right balance of power and voltage flow regulation. In coming up with answers to this puzzle, Samsung has been investing in a process of finding the optimal balance between size and performance through Design-Technology Co-Optimization (DTCO) analysis. The goal with DTCO analysis is to investigate ways to optimize overall performance, power reduction and area use (PPA) for transistors, both in process and design. Performance for transistors is measure by whether larger currents can be properly converted into an increase in operating speed. Improving performance, then, is minimizing any factors from chip design that can impede performance. With MBCFET™, performance loss by channel width and deterioration caused by low power, both must be accounted for. DTCO helped developed solutions that not only resolve inefficient structure with building up FinFET channel width, but also the much larger operational current flow for MBCFET™ by allowing for large current flow even at low operating voltage. With regards to area, logic points to an overall reduction of transistor parts as a solution. However, each part in a transistor requires a minimum area to function optimally and changing the size affects the resistance and capacitance of transistors. Any solution, therefore, must take into consideration the complications that might be introduced as a result of scaling, including power overflow and performance decrease. Through DTCO, Samsung has developed channel widths in four options which can be used to balance performance and power reduction matched to the needs of the customer. SRAM wordline driver cases, as an example, can benefit from saved area of smaller channel widths. Variable channel width also means Samsung can provide multiple FF cells such as conventional FF, low power FF, and high-speed FF as better solutions compared to 4nm. And, with feedback loops, using only half of the cycle compared to previous circuits can save on power. Ultimately, thanks to DTCO, Samsung Foundry customers can benefit from faster development of nodes at lower costs. Providing Proven Design Infrastructure with Samsung Partners

The advantages gained from DTCO were made possible thanks to the assistance from the Samsung Advance Foundry Ecosystem (SAFE) – a comprehensive program that brings together the Samsung Foundry, its ecosystem partners and customers to offer cutting-edge System on Chip (SoC) designs. Designed to get customers to market faster, improved sign-off process, and product reliability, SAFE works with industry partners like Ansys, Cadence, Siemens, and Synopsys to develop innovative solutions to optimize semiconductor designs. Through its synergic network, SAFE provides customers competitive foundation IPs through 56 IP partners with more than 4000 IP titles, fundamental RTL-to-GDS design methodology documents through EDAs, and a more-flexible design environment with access to cloud service providers such as AWS and Microsoft Azure.