Meeting the Growing Semiconductor Needs with Ingenuity, Optimized Design Solutions and Industry Partner Support

Over the past two decades the number of transistors in the world has increased over 1000 times. That incredible growth stems from the tremendous increase of computational requirements in various tech sectors. It has also led to immense growth in the semiconductor industry – culminating in a $600 billion uptick in the market in 2021. But while satisfying those new demands requires vast quantities of chips, more important is the wave of innovation it has triggered, leading to massive leaps forward in technology and the way we create products. With newer chips growing in performance and shrinking rapidly in size, we're quickly approaching the reticle limit. As a solution, Samsung Foundry has introduced three effective ways to meet the needs of the growing semiconductor industry while advancing it forward: Gate-all-around (GAA) technology, multi-die integration, and a complete design platform for seamless production.

Overcoming FinFET Size, Performance Limitations with GAA Decades after the industry’s move from planar to fin field-effect transistor (FinFET), the multigate device still served as a standard in chip design. FinFET’s advancement, however, hit a theoretical wall with the number of fins deciding channel width. Those restrictions on size also translate to limitations on performance. With the development of GAA, that problem was circumvented. Thanks to its stacked design, GAA technology allowed for a more flexible application. This is because, unlike FinFET, for GAA, the nanosheets themselves decide channel width, opening the doors for power, performance and area (PPA) improvements. Samsung’s GAA processes are available in various sizes multiple nanosheet configurations. For example, for 3nm processes, there are four nanosheet width (NSW) options from NSW1 to NSW4. Categorized by use-cases in relation to frequency and power, these configurations range from Ultra High Density (UHD) Cell with NSW1 and NSW2 options, High Density (HD) Cell with options from NSW1 to NSW3, and High Performance (HP) Cell containing all options NSW1 to NSW4. In terms of PPA, there are improvements in frequency and reductions in power consumption with each step up in nanosheet width. Along with NSW flexibility, there have been improvements made with the enabling of rectilinear shape cells to save more area and the utilization of machine learning based Electronic Design Automation (EDA) solutions for better implementation flow. These improvements have presented some impressive results. With the performance and power improvements of GAA as well as the Samsung Foundry’s DTCO, designers can easily find the PPA sweet spot for whatever design best suits their needs.

Multi-die Integration for High Power Design Solutions Apart from our GAA solution, Samsung has also prepared 2.5D and 3D design solutions enabling multi-die integration on an interposer to overcome size limitations. In 2.5D solutions, Samsung provides high-power design solutions for up to 1kW HPC application with the use of the integrated stack capacitor with 1uF/mm2 capacitance, HPC applications that can accommodate up to 8 HBM3 at 6.4Gbps speed as well as various chiplet IP solutions, such as HBB(High Bandwidth Bridge), serial D2D(Die to Die), and BOW(Bunch of Wire). In addition, Samsung is also currently developing chiplet IP solutions for 3nm. When developing 3D IC solutions, it is important to consider the effects of high-density D2D interconnects and numerous through-silicon vias (TSV). As such, we offer a 9TSV bundle by grouping distributed TSVs, placing passive devices in keep-out-zone, and provide 3D-specific SRAM macro. With these design solutions, the bottom die can be more efficiently designed. And with the utilization of a corner compaction methodology for efficient multi-die signoff, we’ve decreased turnaround time.

Total Design Platform in Collaboration with Ecosystem Partners Finding lasting solutions in any technical field requires more than just one-off technology advancements. It requires complete support. On that account, Samsung Foundry has developed a total design platform to meet the growing needs of its customers. Samsung's Total Design Platform embeds the best-known methodologies and IPs combined with process and package solutions. It offers collaborative insights from our Samsung Advanced Foundry Ecosystem (SAFE) partners in mobile, automotive, and HPC/AI, who develop design infrastructures with Samsung. The benefits of Samsung’s design platform can be best explained in the real-world advantages it provides. In mobile applications, to save power and area, we provide a customized flip-flop and SRAM that lowers Vmin to below 0.5V. In addition, we also provide machine learning based P&R solutions. For the automotive sector, our qualified IP and design solutions are offered as a safety measure to prevent failure while driving. This includes IP for real-time monitoring of frequency, power, and temperature along with advanced DFT solutions. In practice, this reliable implementation enabled one product to run 24 hours a day for 10 years. Finally, for HPC, Samsung provides high performance infrastructure such as uLVT cell, UHS SRAM, and 6.4Gbps HBM3 interface. By leveraging 32Gbps D2D interface, it's possible to implement two logic dies and eight HBM. SAFE has been growing year after year with new partners joining our open ecosystem. We are currently engaged with 22 EDA partners, 9 DSP partners, 10 OSAT partners, 9 cloud partners, plus, 56 IP partners who provide more than 4,000 IP titles. This is only the beginning of what’s possible with GAA and multi-die integration solutions. With the support of Samsung’s ecosystem partners, Samsung Foundry will continue striving to offer the best possible support for our customer´s success by expanding our design infrastructure to meet ever-growing needs in the semiconductor industry.