Today, the automotive industry is on the cusp of a major electrical and electronic (E/E) architecture change. What is driving this change? Simply put, the traditional distributed architecture used for decades is not suited to process the increasing amounts of data from new systems and cannot support software defined features.
So, what is the solution? Centralized architecture. This solution consolidates various functions separated throughout the vehicle in distributed and domain architectures (ADAS, IVI, etc.) into a single, centralized module. Instead of the systems being isolated or separated, all functions within a region of the vehicle are connected to a zonal gateway. Each gateway, in turn, is connected to other zonal gateways and the high-performance, centralized SoC(s) via a multi-Gig Ethernet channel. See
the previous tech blog for more details on centralized architectures.
In addition to the performance increase, centralized architecture has a cost benefit. First, the use of a common ethernet backbone for all functions eliminates dedicated cable harnesses required for each function or domain. Next, as functions are consolidated into centralized SoCs, the total number of SoCs and ECUs decreases. It is estimated that a vehicle with centralized architecture has 20% fewer SoC/ECU(s) and 10% lower hardware and material costs.1
Aside from the performance requirements, centralized architectures will be running safety-critical functions such as braking and collision avoidance. These applications require unique safety requirements to ensure data integrity and reliability in harsh environmental conditions. Enduring extreme temperatures and mechanical stress is essential to safeguarding operation in safety-critical functions. Furthermore, in a centralized architecture design where functions are consolidated, memory is a shared resource among previously isolated functions. As such, the memory must support the required safety level of each function it supports.
These changes will have a profound impact on system memory requirements.
Originally developed for mobile phones due to its low-power and high-performance characteristics,
LPDDR DRAM is an ideal choice for automotive centralized architectures. As greater volumes of data are generated through autonomous driving features, high-bandwidth LPDDR memory is needed to process massive amounts of vehicle data at much faster speeds.
Samsung recently released its newest automotive-grade version of the LPDDR5X, which is manufactured on the most advanced 12nm-class technology node in production with a highly competitive cell size2. This new addition to the automotive portfolio provides higher performance and power efficiency while maintaining form, fit, and function compatibilities with previous LPDDR5/5X products.
The LPDDR5X is the ideal product suited for today’s automotive SoCs due to its high-performance, safety-critical systems with up to a 9600Mbps data processing speed, a wide-range of densities spanning 3GB to 24GB, and three different JEDEC-standard FBGA packages, including a new 561F FBGA that is 50% smaller than the existing 441F FBGA solution. In addition, the 12nm-class Automotive LPDDR5X has been designed and developed for ASIL-D systems, the highest Automotive Safety Integrity Level (ASIL), and for highly demanding automotive application use cases in full compliance with the ISO 26262 standard. Since the LPDDR5X is targeted for the automotive market, it also supports AEC-Q100 qualifications and the Grade 1 (-40°C to +125°C) temperature range.
Performance
The consolidation of functions in a centralized architecture will require SoCs to support the combined workload of previously isolated systems, at a minimum. At the same time, system designers need to ‘future-proof’ hardware in a software-defined vehicle to accommodate new features and applications over the life of the vehicle. Today, automotive SoC suppliers are addressing this by introducing increasingly powerful processors, with some supporting upwards of 1,000 TOPS, where high-performance memory is required to achieve maximum SoC performance.
To put this into perspective, the 9600Mbps performance is for a single I/O. Consider that most SoCs today have a 256-bit bus width and this translates to the 12nm-class LPDDR5X supporting 307.2GB/s memory bandwidth to the SoC. While other memory interfaces may provide a higher I/O bandwidth, they typically come with a premium cost per bit and in some cases, a higher assembly cost.
Safety
To address safety-critical system requirements, OEMs, Tier 1 suppliers, and component suppliers adhere to the ISO 26262 standard for functional safety in automotive E/E systems. ISO 26262 provides a comprehensive framework for managing the safety risks associated with automotive systems throughout their entire lifecycle. The standard outlines processes, activities, and requirements for achieving functional safety, including hazard analysis, risk assessment, and development of safety goals and requirements.
ISO 26262 certification is done during the functional safety management process and at the product level.
Certification during the functional safety management process demonstrates the organization has processes in place to address the risk assessments of a component for its entire lifecycle. Samsung achieved ISO 26262 certification in 2019 through TÜV Rheinland, an international third-party testing, inspection, and certification company.
At the product level, a company must establish through documentation that the product was conceived and developed with functional safety as a cornerstone, from planning, design, and production (through end-of-life). The product then achieves an Automotive Safety Integrity Level (ASIL) for electrical and electronic systems based on random hardware failures, measured by failures in time (FIT).
The ASIL hierarchy is defined in four levels, ranging from ASIL-A, the lowest level of risk, through ASIL-D, the highest level of risk. For example:
An ADAS or AD system will incorporate several of the functions listed in the table, including braking systems, cruise control, and vision ADAS rear view cameras. While each of these functions has a different safety-level, the components used in the central compute module supporting these functions, including memory, must support the highest safety-level (ASIL-D) to ensure all safety requirements are met.
The Samsung Automotive LPDDR5X has been specifically developed from the initial planning stage to meet the highest safety requirements of automotive systems. ASIL-D is the highest classification of initial hazard defined within ISO 26262 and represents severe life-threatening or fatal injuries, meaning that the highest level of safety assurance is required to meet the safety goals of ASIL-D certification. The Automotive LPDDR5X is expected to achieve ASIL-D enhanced functional safety levels, including Assumption of Use (AoU), developed using ISO 26262 SEooC (Safety Element out of Context) concept where the host performs self-correction for single bit errors and self-detection for multiple bits errors.
Small Package
As mentioned above, the Automotive LPDDR5X will be available in three JEDEC-standard packages. The 315F FBGA, which supports a x32 bus, and the 441F FBGA, which supports a x64 bus. A new 561F FBGA with a x64 bus interface is also available. The 561F FBGA at 8mm x 12.4mm (99.2mm2) is approximately 50% smaller than the 441F FBGA with package measurements of 14mm x 14mm (196mm2).
With centralized architectures requiring higher performance memories to operate across automotive temperature ranges, signal integrity becomes a challenge. While signal routing depends on various factors including PCB material and component specifications, in general, minimizing trace lengths reduces interference and crosstalk, thereby improving signal integrity. The advantage of the smaller 561F FBGA is that it allows packages to be placed physically closer to the SoC to ensure the shortest signal traces and provide the best signal integrity.
Additionally, the smaller size and ball pitch of the 561F package makes it the ideal package solution for Multi-chip Module (MCM) integration, wherein multiple ICs, including SoC and memory, are placed on a small substrate with the goal of optimizing electrical performance. In addition to improved signal integrity, the close proximity of ICs to one another in an MCM enables a close communication channel resulting in improved performance due to minimal delay.
Designing in a JEDEC standard package, such as the 561F FBGA, provides a single PCB layout that allows automotive customers to scale up or down memory densities to cost-effectively tailor features for each trim/model. In addition, packages based on an industry trade organization ensures customers will have multiple vendors to choose from rather than design in a single-source, a necessity for supply chain stability.
Helping to architect the future
As automotive vendors and manufacturers push the boundaries of innovation, the need for highly reliable, high-performance memory solutions becomes critical. With the consolidation of functions and compute-intensive systems (ADAS/IVI) into a centralized architecture, onboard compute requirements have grown exponentially and will continue to. This necessitates the need for high-bandwidth, low-power DRAM solutions, to meet the demands of real-time data processing.
For decades now, Samsung has been one of the industry’s leading providers of memory solutions for data centers, mobile, IoT, and consumer electronics, and is now bringing that same track record of trust and innovation to the automotive sector. Samsung’s comprehensive portfolio of automotive memory products is the ideal solution for customers who need to achieve functional safety goals with confidence, defined by high fault coverage, enhanced safety mechanisms, reliability, and uncompromising quality.
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