Samsung solidified its leadership in the NAND flash market by commencing production of the industry's first “1Tb (terabit) TLC (Triple Level Cell)* 9th generation V-NAND” in April. It boasts approximately 1.5 times higher bit density* than the previous generation, thanks to the implementation of industry’s smallest cell size and thinnest mold*. It features technologies such as cell interference avoidance and cell life extension to control interference phenomena* and enhance product speed, power efficiency, quality, and reliability.
Today, the newsroom had the opportunity to meet with Jay Hyun, the Corporate VP of Product Planning, Seungwan Hong (Corporate EVP), Eunkyoung Kim (Corporate VP), and Jiho Cho (Corporate VP) of Flash Product & Technology. These individuals are responsible for the planning and development of the revolutionary 9th generation V-NAND. Join us as we venture into the world of Samsung V-NAND and discover the exciting possibilities it brings in the era of AI.
Q. What role does Samsung NAND flash play in the era of hyperscale AI?
Jay Hyun, Corporate VP
In the AI era, various solutions are required in addition to High Bandwidth Memory (HBM), which supports high-speed parallel computing for the data training of language model. There must be space to store the large-scale data used for training, and high-performance storage is also needed for the algorithms to operate quickly during the inference stage. Samsung's NAND flash plays a central role in implementing these key elements. Samsung V-NAND is expected to contribute to the delivering of accurate and fast AI services as a high-performance storage.
Q. What are the features of the “1Tb TLC 9th Generation V-NAND”?
Seungwan Hong, Corporate EVP
The 9th-Gen V-NAND is NAND flash memory that has increased its density since its 1st generation of V-NAND, which was the world's first mass produced 3D vertical structure in 2013 by Samsung. By increasing the storage space density by more than 1.5 times compared to the previous 8th generation, it has implemented approximately 1 trillion bits of cells within a single chip. It boasts a maximum data transfer rate of 3.2Gbps, which is 33% faster than previous product, and a power consumption improvement of over 10% by applying the latest design technology. Additionally, it achieves the highest number of stacks in the industry with a “double stack” structure.
Jay Hyun, Corporate VP
The 9th-Gen can be considered as a big node that can stably supply a full lineup from high-performance TLC (Triple Level Cell) applications to high-capacity QLC (Quadruple Level Cell)* applications in one generation. It was also an opportunity to prove Samsung's TAT (Turn Around Time)* competitiveness in the market. As a solution introduced to satisfy the recovering demand and enhance market prominence through domestic and overseas production site, we expect that it will strengthen our technological leadership and meet customer needs.
Q. How has technical expertise contributed to the development of the unique features of the 9th-Gen V-NAND, like its smallest cell size, thin mold thickness, and channel hole etching technology?
Seungwan Hong, Corporate EVP
Samsung has developed and applied various technologies in the 9th-Gen, including process design (Integration) technology that allow for maximum stacking of layers with the smallest possible stack, device scale-down technology, and contact etching* technology with the highest aspect ratio* within the minimum area.
Some terms may not be familiar, but to get closer to comprehending the 9th-Gen, it is important to understand V-NAND itself. Generally, V-NAND stacks cells by cross-stacking thin layers made of chemical compounds called 'oxide' and 'nitride.’ Then, it replaces nitride with a metal material to form the cell gate word lines. The unit that binds the stacked oxide and nitride together is called a “pair,” and this pair can be considered as one “layer.” The number of pairs stacked determines the level of NAND. As more of these pairs are stacked one on top of another, the level or layer of NAND increases.
The structure in which pairs are bound, known as the “mold,” has a total height that can be etched at once, so it is important to make each pair thin. However, as the pairs become thinner, cell interference becomes more serious, requiring technology to control it. This is where Samsung solutions come into play. Samsung has applied the industry’s thinnest “Cell Gate Word Line Formation Process Technology” to make each pair thin and utilized design technology to control the cell interference. Additionally, by enhancing “HARC(High Aspect Ration Contact) Etching* Process,” uniform channel holes are formed from top to bottom. Through these process innovations, we were able to achieve the industry’s highest level of NAND with the minimum mold thickness.
Q. What is the secret behind the high quality of the 9th-Gen V-NAND, and what specific know-how has enabled its early success in mass production?
Eunkyoung Kim, Corporate VP
Samsung has been able to identify and address the vulnerabilities of various products by implementing numerous verification, evaluation, and defense systems. We have also accumulated diverse capabilities and know-how through self-development efforts. The early success of 9th generation V-NAND mass production was attributed to engineers' full dedication to uncovering and addressing the layered issues accumulated during the early stages of development.
We thoroughly prepared alternatives for anticipated scenarios, not only through various technical attempts aimed at precisely probing the issues, but also by adjusting internal workflows within the organization.
Moreover, we diligently conducted a thorough analysis and prediction process, persistently examining each issue until the phenomena, levels, and characteristics appearing from the root to the subsequent productization stages were thoroughly contrasted. Throughout this process, product and process engineers collaborated closely, objectifying all information.
We were able to secure quality control capabilities successfully during the fab process and electrical testing stages. The collaboration with the Quality & Reliability office, where they thoroughly understood the technical strategy of the Flash Product & Technology Office and executed it together, was greatly beneficial.
Q. What innovations have taken place in the transition from previous generation?
Seungwan Hong, Corporate EVP
There were some challenges in which the support pillars, responsible for preventing the collapse of the mold, would stick together due to the reduction in chip area. Additionally, there were selectivity limitations of the contact (*CMC : Cell Metal Contact) etching technology, which ensures safe landing or stopping on from the top to the bottom of the cell gate word line.
To address the fundamental challenges that arose in previous generations, “Through Cell Metal Contact (TCMC)” technology was adopted to 9th-Gen for the first time in the world. This technology involves piercing through the cell gate word line from the top to the bottom, allowing only selected word lines to be activated. In addition to that, a structural innovation was achieved by etching different types of contacts* together in a single etching process (HARC Etch Merge), enabling one contact to perform two different roles. This was the world's first attempt to make impossible work possible, so it required numerous challenges, trials and errors, engineer efforts, collaboration, and innovative ideas from product development to mass production.
Moreover, through the innovative process design technology that divides word lines while removing dummy channel holes*, the 9th-Gen has significantly increased the bit density within the same planar area.
Jiho Cho, Corporate VP
In the AI era, the demand for high-performance and high-capacity memory has increased exponentially due to the escalating performance requirements of CPUs and GPUs. While the power consumption necessary for achieving high performance has also increased, the implementation of such high-performance capabilities has become more challenging due to power constraints imposed by the permissible power limits set for different applications.
So we focused on “Low power design technology” in the 9th Gen V-NAND. It was designed to minimize power consumption by lowering operating voltage of external/internal voltage(EVC/IVC) and I/O external/internal voltage (VCCQ/IOIVC) used to operate the NAND cells. Additionally, innovative circuit layout techniques have been applied to minimize the distance of internal data movement and reduce the load.
Furthermore, I would like to mention the “Word Line Charge-discharge Efficiency Technology” and “Selective Bit Line Voltage Charging Technology.” Firstly, the “Word Line Charge-discharge Efficiency Technology” reduces the number of charge-discharge cycles of the world lines, thus efficiently utilizing the charged power. Since the movement of charges is directly related to power consumption, the charge-discharge operations themselves result in power consumption. By reducing the movement of charges, power consumption is correspondingly reduced.
The “Selective Bit Line Voltage Charging Technology” is another important aspect that has helped reduce power consumption during the read operation of the cells. In the 9th generation, a fundamental innovation has been achieved by enabling charging and sensing only on the required bit lines*. With the application of these innovative design techniques, 9th-Gen has achieved more than a 10% improvement in power consumption compared to previous products.
9th-Gen V-NAND cells are at the industry’s minimum size level. Generally, minimizing cell size makes it challenging to overcome reliability degradation* and interference issues. As the cell size decreases, the ability of the cell to hold charge also weakens. Moreover, interference issues can occur when cells are densely packed in a confined space. To overcome these limitations, we implemented the technology inside the NAND chip that automatically tracks the optimal read point based on the number of cell write-reads and retention time. In other words, we've implemented design techniques on the chip that automatically determine the level of degradation of the cells.
Eunkyoung Kim, Corporate VP
We achieved our targeted quality quickly by focusing all of our engineering skills on screening out short-lived chips statistically during the electrical test phase accurately and ensuring the quality data for machine learning. To track the properties of defects accurately, we redesigned the stimulating factors and test items in more detail compared to the previous generation product. All types of defects were statistically classified and segmented 100%, while establishing clear correlation between the fab process and electrical testing stages on a wafer-by-wafer basis. Furthermore, we tracked the changes and properties of defects through subsequent quality evaluations.
In particular, in the 9th-generation V-NAND, data mining technology that combines Samsung Electronics' semiconductor expertise with machine learning played a major role in interpreting electrical evaluations.
To predict the possibility of defects occurring in wafers, chips, and blocks at an unspecified future time, many technologies have been accumulated, and the accuracy of this prediction was truly remarkable in the product.
Q. Why is there a focus on high-capacity NAND flash, including the upcoming QLC announcement in the second half of the year?
Jay Hyun, Corporate EVP
There are three main reasons for the increasing interest in high-capacity storage servers for AI applications. Firstly, there is a need for high-capacity memory per storage server due to the power cost limitations in AI data centers. Secondly, there is an increased demand for high-performance and durable storage due to the growing importance of maintaining checkpoints*. Lastly, the demand for high-performance storage is driven by the proliferation of multimodal AI models*. Due to these trend, the market's interest in high-capacity NAND flash memory is currently increasing. Samsung plans to develop QLC-based products to respond to the high-capacity storage market for AI.
Q. How do you forecast the future trends of the NAND flash market?
What is Samsung’s strategy in response to these trends?
Jay Hyun, Corporate VP
The NAND flash market has grown alongside the emergence of killer applications such as MP3 players, smartphones, cloud services, AI, and advancements in data transmission technology. In the future, more storage will be needed to process the data of machines that learn on their own beyond generative AI. Therefore, we expect the NAND flash market to continue to grow in the mid to long-term perspective.
Our goal is to develop products that can satisfy customer demands by reading market trends and delivering them in a timely manner. We are strengthening our portfolio by focusing on AI server products and expanding into next-generation applications such as On-Device AI, automotive, and edge devices, which are expected to be important in the near future.
Another goal is to contribute to the well-being of humanity and enable sustainable growth through the advancement of semiconductor technology. We are committed to continuous efforts in developing high-capacity and low-power eco-friendly (carbon reduction) technologies.
Q. Any comments for the readers of the Samsung Semiconductor Newsroom?
Seungwan Hong, Corporate EVP
The main reason we were able to mass-produce the 9th-generation V-NAND for the first time in the world is that the capabilities of all members from each team of the Memory Business and Semiconductor R&D Center were fused together as 'One Team' to maximize synergy. By continuously generating and evaluating a variety of innovative ideas for implementing advanced processes, we tackled each defect we encountered one by one, and ultimately created a completely new process that had never existed before.
NAND flash technology is evolving to meet the customers’ demand for high capacity and high performance. In order to achieve this, Samsung will continue to innovate through technologies such as “minimizing the number of HARC etching process” per stack, high-performance semiconductor manufacturing through “High-K Metal Gate(HKMG),” and various combinations of “Multi-Bonding technology.
Jiho Cho,Corporate VP
I have been responsible for flash memory design since I joined in 1998, and it has been at critical turning points up to the present. The 2nd, 4th, and 7th generations of V-NAND, in particular, hold a special place in my memory. The significance of being recognized as the “world’s first” in this 9th generation fills me with great pride. We are preparing for the release of the “QLC 9th generation V-NAND” in the second half of this year. Moving forward, we will strive to achieve the highest performance, reliability, and low-power efficiency in our future next-generation products, further solidifying our position as an industry leader.
Eunkyoung Kim, Corporate VP
First and foremost, I would like to express my gratitude to the team members who have worked together to successfully mass-produce 9th-Gen V-NAND. We anticipate that this product, boasting overwhelming performance, features, and quality, will play a central role in the market. Leveraging the experience gained from this production, we will strive to develop other 9th generation products in a timely manner and make them the best in terms of competitiveness in all aspects.
Since becoming the world’s number one in NAND flash memory in 2002, Samsung has been leading the market and introducing groundbreaking technologies. Following the successful 9th-Gen V-NAND mass production, which can be considered the fruit of a long journey, Samsung plans to continue shaping a sophisticated future through relentless innovation and the development of cutting-edge memory technologies.
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