The Evolution of AI-Era Memory: Faster, Denser Computing

Samsung Electronics showcases its vision for next-generation 3D memory at FMS 2026

AI is rapidly advancing from generative AI that simply answers questions to agentic AI capable of planning, reasoning and acting on its own. As a result, the volume of data AI needs to process is growing far beyond what it once was. As context windows and reasoning chains grow longer, not only does the amount of data AI generates increase, but so does the size of the KV cache, which stores previous conversation history and intermediate computation results for use in the next task.

With AI now handling far larger volumes of data, the factors that determine AI system performance are shifting as well. Today, an AI infrastructure’s core competitiveness depends not only on processor performance, but on how efficiently it can store massive amounts of data and how quickly and reliably it can deliver that data to an AI accelerator.

Addressing this shift requires more than simply increasing memory speed and capacity. The entire memory architecture must be reimagined, from the memory-to-processor interface and chip stacking technology to the cell architecture itself.

Samsung’s zHBM, zNAND-O and V10 BV-NAND, unveiled at FMS 2026, represent next-generation 3D memory technologies designed to address these demands. Each addresses a different bottleneck in AI data centers and on-device AI environments, pointing the way toward higher performance and greater power efficiency.

Bringing data closer to unlock AI performance: zHBM

The performance of an AI chip isn’t determined by computing power alone. No matter how capable a processor is, overall system performance is inevitably limited if it doesn’t receive the data it needs in time. As AI models grow larger, the volume of data moving between memory and the processor increases sharply, making it more important than ever to shorten the distance between the two.

To address this challenge, Samsung introduced zHBM, a new architecture that differs from conventional HBM. Instead of placing memory beside the AI accelerator (xPU), zHBM stacks memory directly on top of the processor. By shortening the distance data must travel, the architecture delivers higher bandwidth and improved power efficiency.

Supporting this architecture, Samsung applied Hybrid Copper Bonding (HCB), which enables highly precise copper-to-copper bonding, along with Multi-Wafer Bonding, which bonds multiple wafers into a single structure. Together, these technologies increase signal transfer speed while reducing thermal resistance, creating a more stable operating environment. They are also expected to improve the training and inference performance of large-scale AI models while making AI services more responsive.

Powering on-device AI: zNAND-O

The way AI is being used is evolving as well. While AI computation has traditionally taken place on cloud servers, on-device AI is rapidly expanding, bringing AI capabilities directly to devices such as smartphones and PCs.

On-device AI requires storage that can deliver high performance and power efficiency even within a limited footprint.

Samsung’s zNAND-O is a next-generation NAND solution built to meet this need. It applies a 3D packaging technology that vertically stacks multiple V-NAND chips through TSVs, delivering both high storage density and high data-loading bandwidth.

This enables AI features to run entirely on the device without a cloud connection, allowing even advanced models to process data locally without sending it to external servers, thereby significantly enhancing user privacy.

Stacking higher, storing more: V10 BV-NAND enters the 400-layer era

In the AI era, the amount of data that needs to be stored is also growing rapidly. Fitting more data into a storage device of the same size requires stacking memory cells even more densely.

Samsung’s 10th-generation V-NAND, V10 BV-NAND, marks the next evolution in V-NAND technology with an ultra-high layer count exceeding 400 layers. By stacking memory cells vertically across more than 400 layers, it stores more data within the same footprint.

This is made possible by its bonding architecture. Memory cells and peripheral circuits were previously manufactured together on a single wafer. V10 BV-NAND instead manufactures memory cells and peripheral circuitry separately on two different wafers before precisely bonding them together. This minimizes structural limitations associated with ultra-high stacking and delivers roughly 58% higher memory density than the previous generation (V9). Samsung also adopted a process better suited to peripheral circuit fabrication, minimizing power consumption during operation while improving performance.

As V10 BV-NAND is adopted in SSDs and other products, it is expected to enable large storage capacities even in thinner, lighter devices. In data centers in particular, it can help improve operating efficiency by storing more data in the same space while reducing power consumption and heat generation.

The future of AI memory: Closer to the processor, greater density

The three technologies Samsung Electronics unveiled at FMS 2026 serve different purposes, but share a common direction: a three-dimensional “Z-axis” strategy that shortens the distance between memory and the processor to minimize data movement, while maximizing storage capacity and performance within a limited footprint.

As AI technology continues to advance, memory is evolving beyond simple storage to become a core driver of computing performance. Samsung’s next-generation 3D memory technologies offer a glimpse into the future of memory architecture across diverse computing environments, from AI infrastructure to on-device AI.

Looking ahead, Samsung Electronics will continue strengthening its integrated capabilities across memory, foundry and advanced packaging. Building on these strengths, the company aims to develop next-generation semiconductor technologies optimized for the AI era.