Though the solutions for overcoming nanowires-based GAA architecture limits may seem straightforward, it required finding the right balance of power and voltage flow regulation. In coming up with answers to this puzzle, Samsung has been investing in a process of finding the optimal balance between size and performance through Design-Technology Co-Optimization (DTCO) analysis.
The goal with DTCO analysis is to investigate ways to optimize overall performance, power reduction and area use (PPA) for transistors, both in process and design.
Performance for transistors is measure by whether larger currents can be properly converted into an increase in operating speed. Improving performance, then, is minimizing any factors from chip design that can impede performance. With MBCFET™, performance loss by channel width and deterioration caused by low power, both must be accounted for. DTCO helped developed solutions that not only resolve inefficient structure with building up FinFET channel width, but also the much larger operational current flow for MBCFET™ by allowing for large current flow even at low operating voltage.
With regards to area, logic points to an overall reduction of transistor parts as a solution. However, each part in a transistor requires a minimum area to function optimally and changing the size affects the resistance and capacitance of transistors. Any solution, therefore, must take into consideration the complications that might be introduced as a result of scaling, including power overflow and performance decrease. Through DTCO, Samsung has developed channel widths in four options which can be used to balance performance and power reduction matched to the needs of the customer.
SRAM wordline driver cases, as an example, can benefit from saved area of smaller channel widths. Variable channel width also means Samsung can provide multiple FF cells such as conventional FF, low power FF, and high-speed FF as better solutions compared to 4nm. And, with feedback loops, using only half of the cycle compared to previous circuits can save on power.
Ultimately, thanks to DTCO, Samsung Foundry customers can benefit from faster development of nodes at lower costs.
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