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[SAFE Forum 2023] Samsung Foundry Accelerates the Speed of Innovation

This is the first article of a two-part series about Samsung Foundry, highlighting the key sessions at the SAFE™ Forum 2023. The series deals with technologies and advancements in the SAFE™ ecosystem.

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On June 28th, hundreds of Samsung Foundry partners and customers from around the world gathered to attend the Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023 in San Jose, CA. Following the Samsung Foundry Forum (SFF) 2023 that took place the previous day, this event was held under the theme of “Accelerate the Speed of Innovation”. It served as a platform for key members of the Samsung Foundry ecosystem to share progress and engage in technical sessions covering the latest industry trends and SAFE’s efforts to ensure industry-leading customer experiences.
Jongwook Kye, EVP and Head of Foundry Design Platform Development at Samsung Foundry, delivered the forum's Welcome Remarks, touching on Samsung Foundry’s innovative journey, the company’s unwavering focus on collaboration, and plans to accelerate the next wave of innovation.
In his speech, he said, “SAFE™ has grown by leaps and bounds and has become a fully symbiotic ecosystem benefiting all its members. At Samsung Foundry, we build technologies for our customers and partners to help them bring the next level of innovation to fruition. The technologies are further boosted by our advanced ecosystem, which provides enhanced convenience and collaboration.”
SAFE™: The Robust Base of Foundry The Samsung Advanced Foundry Ecosystem, commonly referred to as SAFE™, is a holistic ecosystem that enhances synergy between Samsung Foundry and its partners and customers, with the ultimate goal of producing more powerful, efficient, and advanced system semiconductors. Building on last year’s SAFE™ Forum, which established Foundry’s role as an “Innovation Catalyst,” this year’s event emphasized a drive toward the acceleration of innovation in the industry. “The next phase of innovation has started, and we’re going to do everything we can to accelerate it, driving the realization of new silicon innovations like nanosheet technology and expediting faster adoption of cutting-edge solutions,” said Kye. He then stressed the importance of the five pillars of SAFE™ — IP, EDA, OSAT, DSP, and Cloud — which are fundamental to Foundry’s continued delivery of exceptional customer service.
IP Portfolio Expansion Samsung has announced an IP portfolio expansion for advanced nodes and mainstream nodes, with multiple SAFE™ partners making significant investments to extend IPs to customer use. For chiplet-based high performance computing (HPC), Foundry is building multiple high-speed I/Os with its IP partners, and several key nodes have been qualified as Automotive Grades 1 and 2.
EDA Advancement For EDA, Samsung has worked with 23 partners to optimize solutions for various applications — from mainstream nodes to advanced nodes. — and in Samsung process technologies, more than 80 tools have now been certified. The company is also working on further collaboration for easier node-to-node, fab-to-fab, or RTL-to-RTL1 migrations. These types of seamless migrations are becoming increasingly necessary in a climate of rising design costs. In addition, there are plans in motion to reduce costs by enabling easier migration through AI engines, with generative AI showing the potential to reduce turnaround times for design.
Substantial Progress for DSPs and OSAT On a global level, Samsung Foundry is working for eight DSPs to expand design services. These partners are increasing their own capabilities to better serve Samsung’s customers and have shown a great willingness to collaborate. What’s more, by building test chips for DSPs with extensive capabilities, Foundry can ensure higher levels of product deployment and customer satisfaction. The company is also providing cost-effective solutions for OSAT partners, including 2D, 2.5D, 3D, and other technologies.
Samsung Brings 3DIC Ecosystem, Multi-Die Integration Alliance, and 3DCODE In an environment where Moore’s Law is slowing down, the 3DIC ecosystem has become particularly crucial since the industry needs to prepare for the next phase of its evolution. Samsung has identified 3DICs as the future of semiconductor products like networking, HPC, and even mobile applications. As such, the company announced at SFF 2023 the Multi-Die Integration Alliance — which allows members to enable the facilitation of 2.5D and 3D package designs for customers. The alliance features multiple partners from a wide variety of areas, extending from Foundry, EDA, IP, DSP, and package to test, memory, and substrate. These key partners are now collaborating on fan-out packaging2, which is already in use for mobile applications, and I-Cube3, which Samsung is developing for HPC. Going a step further, X-Cube4 will soon be available for a wide range of different applications, moving from simple to complicated integration. The 3DCODE standard, which is a system description language intended to simplify the definition and interoperability of design creation and analysis flows in a unified environment, was also announced at the event. This new standard ensures better experiences for designers creating advanced packaging technologies.
Kye summarized Samsung Foundry’s comprehensive strategy by emphasizing that a collaborative approach would result in a faster technological evolution and mutual success. He remarked, “The industry will face new challenges, but these challenges can also be new opportunities. We’ve always found a way to overcome hurdles through innovation, and now it’s time for us to prepare for the next step, together.” Informative Presentations on Advanced Technology & Solutions
The Welcome Remarks were followed by four keynote speeches, including three guest speakers from Ansys, Alphawave, and IBM, in the morning and two tech sessions in the afternoon. The forum also provided a partner pavilion with 40 booths for networking opportunities.
In the afternoon, the tech session titled, “Advanced Technology and Design Infrastructure” was led by Sangyun Kim, VP of Design Technology, while “Advanced Design Solutions for HPC and Automotive” was presented by Jongshin Shin, EVP of IP Development. These two sessions will be covered in greater detail in part two of this series. To learn more about SAFE™ Forum 2023 or to watch the keynotes & tech sessions, visit the event webpage.
1 Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices. 2 Fan-out packaging refers to any package that has connections fanned-out of the chip surface to enable more external I/Os. 3 I-Cube™ deploys parallel horizontal chip placement to boost performance while combating heat build-up. 4 X-Cube™ features significantly shorter signal paths between dies for maximized data transfer speed and energy efficiency.