As semiconductor process technology scaling known as “Moore’s Law” is slowing down, we are
currently facing many challenges and limitations. With heterogeneous integration and advanced
packages, we can significantly reduce costs for design, development, and manufacturing to move forward to “Beyond Moore”.
Closely aligned not only with our own divisions such as Memory, Foundry, and System LSI, but
our Multi-Die Integration Alliance
partners, Samsung will fully support our customers from preparing design infrastructure, designing chiplets, multi-die fabrication, manufacturing interposer, sourcing substrate, all the way to testing completed products, or even sourcing and integrating memory if needed.
Just bring your ideas, architectures, or design, and we will take care of the rest.
I-Cube deploys parallel horizontal chip placement to boost performance while combating heat build-up. Samsung’s Through Silicon Via ( TSV ) and Backend-of-the-line ( BEOL ) technologies form a foundation for two or more chips to harmonize their specialized functions, becoming more than the sum of their parts to deliver powerful solutions for modern devices. I-Cube is available in I-CubeS and I-CubeE derivatives based on the interposer type.
3D IC packages boost performance even further by using much shorter interconnect wire lengths by stacking components vertically, enabling ultra-high vertical interconnect density with lower parasitics while saving massive amounts of on-chip real estate. 3DIC: X-Cube technology dramatically reduces yield risks from large monolithic dies with 3D Integration that enables high system performance with lower cost, while retaining high bandwidth and low power. Samsung’s micro bump based 3DIC technology was developed for HBM, and it has successfully produced tens of millions of HBMs. This is a mass-production-proven and cost effective 3DIC technology. In comparison to micro bump (TCB), a bumpless hybrid copper bonding (HCB) under preparation provides much higher interconnect density and thermal performance, by eliminating the joint gap.
For applications that require a low power memory integration like mobile or wearable devices, Samsung offers two kinds of Fan-out package platforms: panel level package, Fan-out PLP, and wafer level package, Fan-out WLP. Both types of Fan-out packages provide size, thickness, and thermal performance benefits over conventional packages. They provide up to a 40% smaller form factor compared to a flip-chip package, up to a 30% thickness reduction by eliminating the substrate, and up to a 15% thermal performance enhancement by allowing thicker dies.
Samsung has always contributed to the relentless journey of innovation. As one of the founding members of the UCIe Consortium, an industry consortium dedicated to advancing UCIe technology, Samsung will continue to build 3DIC, memory interconnect, and automotive chiplet standards together.
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