World’s First CMM-D Technology Leading the AI Era

The insatiable demand for memory density and bandwidth is pushing the limits of existing memory technologies. Conventional DRAM design limits the scaling of memory capacity beyond a certain range, requiring an entirely new memory interface technology. What’s more, the rise of AI and Big Data has fueled the trend towards heterogeneous computing, where multiple processors of different types work in parallel to process massive volumes of data. In May of 2021, Samsung announced the development of the industry’s first Compute Express Link (CXL™) based DRAM Memory Module (CMM-D). In May of 2022, Samsung introduced the next generation, CMM-D 2.0, featuring the industry’s first 512GB Memory Module, along with high bandwidth and reduced latency. This was a pivotal step in the commercialization and practical application of CXL technology. What Is CMM-D? At the core of CMM-D is Samsung’s DRAM technology with the integrations of the CXL open standard interface developed through the CXL™ consortium. CXL is a high-speed, low-latency CPU-to-device interconnect technology built on the PCIe physical layer. CXL provides efficient connectivity between the host CPU and connected devices such as accelerators and memory expansion devices. The CXL transaction layer is made up of three dynamically multiplexed sub-protocols on a single link. These protocols are CXL.io, CXL.cache, and CXL.mem. When a CXL device is connected to a CXL host, it is discovered, enumerated, configured, and managed through CXL.io protocol. CXL.cache enables CXL devices to access processor memory, and CXL.mem enables processors to access CXL device memory. CXL.cache and CXL.mem protocol stacks have been optimized specifically for low latency. CMM-D Features and Benefits Traditionally, adding memory capacity and bandwidth in a system involves increasing the number of native CPU memory channels. But adding memory channels to a CPU increases engineering complexity and drives up cost. A CXL Type 3 memory expansion device provides a flexible and powerful option to increase memory capacity and increase memory bandwidth, without increasing the number of primary CPU memory channels. CMM-D is a CXL Type 3 device that provides the following memory expansion features and benefits. CMM-D Memory Coherency An important feature of CXL is that it maintains memory coherency between the direct attached CPU memory and the memory on the CXL device, which means that the host and the CXL device see the same data seamlessly. The CXL host has a home agent serving as a manager that uses the CXL.cache and CXL.mem transactions to access the attached memory coherently. This enables the CXL host and CXL device to work on shared data and are guaranteed to see the same copy of a memory location. The home agent does not allow simultaneous changes on the data, so once a change is made – either by the host or the attached device – the home agent ensures that all copies of the data remain consistent. CMM-D Memory Media Type Another major feature of CXL is that it is agnostic of the underlying memory technology as it allows various types of memories to be attached to the host through the CXL interface. Moreover, CXL.mem transactions are byte addressable, load/store transactions just like DDR memory. So, attached CXL memory looks like a main memory to the end application. CMM-D Memory Pooling and Switching The CXL 2.0 specification also supports single-level switching and memory pooling. Memory pooling increases the overall system efficiency by allowing dynamic allocation and deallocation of memory resources. Memory pooling also enables reduction of stranded memory, a common problem observed in server systems.