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The Next Phase of V-NAND Ingenuity

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One of the leading semiconductor technology advancements in the modern era, Samsung’s V-NAND (vertical NAND) has taken the industry from a major production impasse with planar (two-dimensional) NAND Flash storage memory to an expanding world of storage ultra-efficiency. A Skyscraper of Storage Design Considering performance, capacity and power consumption, V-NAND has been one of the most successful technologies since its introduction in 2013. Instead of stretching memory chips along wider and wider tiny-city streets, block after block, V-NAND made it possible to open a door to the equivalent of skyscraper storage design. And it has reshaped the industry! We are in the 6th generation of V-NAND technology (100+ layers), with more to follow, even though some technological hurdles remain. Naysayers have been questioning whether we can continue to expand what has been advancement after advancement in V-NAND specification improvements over the next decade. Our answer is a resounding “YES.”HP But first, a short primer on where V-NAND has taken us so far, and what it brings to the storage domain of the future. V-NAND is a 3D-cell layer-stacking technology where multiple flash memory cell layers are stacked vertically (3-dimensionally) in each and every NAND chip. Highly reliable, these charge trap flash (CTF) cells have been built with 24, 32, 48, 64, 9x and now 100+ (1xx) layers. Samsung’s 6th generation V-NAND added 40 percent more cells to the 9x-layer (5th) generation. Our revamped V-NAND production process also now reduces the number of channel holes needed to connect the cells of a 256Gb die from over 930 million to 670 million. Moreover, each new generation of V-NAND brings with it a significant increase in performance, while using less power. For example, our 6th generation delivers a 10 percent performance gain with 15 percent lower power requirements. One Step Ahead But what about tomorrow? The question remains: can storage manufacturers like Samsung continue to overcome linkage challenges posed by three dimensional storage technology when working with well over 100+ layers? Can the V-NAND towers inside each storage chip continue to rise in a faster, more efficient, power-saving manner even when the number of layers (and therein the technological hurdles) are increasing? Actually, Samsung engineers have been researching these questions for years. Our R&D experts have been one step ahead of the technological challenges and material requirements to economically build V-NAND as a cutting-edge enabler of the highest order. For our 6th Generation of V-NAND, we have introduced a 3-bit, 100+ layer, single stack, 256-gigabit (and now a 512Gb) chip. We have refined our processes so that V-NAND chip sizes are smaller, require less manufacturing steps, and offer as much as 1.4 gigabits per second of speed for moving information from memory to storage and back. Impressive indeed, yet more advancements await. Our Commitment to V-NAND In moving beyond 100+ to 200+ layers, we are looking to stack our cutting-edge V-NAND skyscrapers on top of one another (separated by an insulation layer). We anticipate that this so-called string stacking will likely be the most efficient way to move V-NAND forward, in conjunction with additional 3D process improvements. Our commitment to V-NAND will continue to reshape how data is stored in a wealth of applications from HPC, IoT, and 5G to increasingly sophisticated Clouds, as well as the best solid state drives for enterprise servers and PCs. Our early V-NAND wasn’t just a breakthrough, it was the first of many integrally intertwined process considerations that together are continuing to redefine chip production in a remarkable rebuilding of storage manufacturing.

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