3D IC solutions can only be achieved by using advanced foundry processes – and no discussion of Cube solutions would be completely without mentioning Through-Silicon Via (TSV).
That’s the technology needed to make those wafer-to-wafer connections fast and efficient. TSV is used when building PDN for the top-die in a cube structure and has the critical job of signaling between top and bottom dies, creating the fast connections our customers rely on. Working with TSV creates numerous challenges to overcome. On top of those, we need a power delivery network to support the 3D IC stack through those TSVs and ubumps, all while meeting IR and EM requirements.
Enabling TSV middle and TSV last in the same die is one solution we’ve found to provide a low resistivity option for power delivery. We’ve also enabled various types of TSV bundles to further reduce IR/EM risks for high performance applications. Going further, we minimized TSV and its keep-out zone penalties through stress simulations and silicon validation, then enabled the placement of certain devices into the keep-out zone to reduce the area penalty. Finally, we made our design flow TSV-aware by developing a macro friendly floorplan guide.
Ubump-based bonding is another technology crucial to the 3D IC process. Samsung Foundry's ubump bonding technology has been tested across solutions and approved for mass production, enabling 3D ICs to be implemented in plethora devices at low cost. That allows customers to start by designing 3D ICs with these essential technologies and PDK, DK, IP, DM design infrastructure with minimum hurdles.
A Question of Design
But in the implementation of 3D IC solutions, there’s another key question that does not arise when dealing with flat chips: do we place function blocks on the top, or the bottom?
To help customers answer that question, we’re developing a partitioning methodology for early-stage design in collaboration with our EDA partners. With these methodologies, every DOE can be analyzed for IR drop, while a designer is able to choose the best candidate for their use. The advantages here are massive: starting a 3D IC design with the right partition candidate can make turn-around-time faster than traditional methods.
Despite all the challenges of working in a cube design, we’re still able to create a 3D design with only a few extra steps on top of the conventional 2D design flow. Most of that comes down to the placement of TSV, while aligning the ubump between the top and bottom dies also requires its own step.
To ensure performance meets and exceeds standards, we put a strong focus on testing. We test the top and bottom dies separately first, then move on to testing for IEEE standard 1838 for 3D to ensure optimal die stacking.
“Because this solution provides fundamental 3D test architecture for pre and post bond tests, it not only gives us a chance to make stacked die patterns more efficiently, but also provides us an assurance of quality,” Kim explained to the crowd at SAFE. If testing reveals unexpected defects, Samsung’s smart lane repair solutions can make the necessary changes to improve yields.
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