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Developing the “Industry’s Most Energy-Efficient" Next-Generation MRAM, Selected as IEDM Highlight Paper

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Samsung Foundry Forum (SFF) 2023 took place in Tokyo, Japan, on October 17th and in Munich, Germany, on October 19th. SFF is Samsung Foundry’s largest annual event, where Samsung shares its latest technologies, business strategies, and vision with global partners and customers. Samsung’s eMRAM and MRAM, with both currently at the center of next-generation memory innovations, were a few of the technologies highlighted at SFF in both Munich and Tokyo. Since starting commercial shipment of an eMRAM solution based on the 28-nanometer (nm) Fully Depleted Silicon on Insulator (FD-SOI) process in March 2019, the company has been supplying a flash-type eMRAM solution along with a non-volatile RAM (nvRAM)-type eMRAM that can function as working memory. MRAM is central to Samsung Foundry’s core portfolio, and the extent of its capabilities is discussed in an academic paper Samsung Electronics published on the subject. Samsung Electronics’ Core MRAM Technology: A Paper Highlighting IEDM In December 2022, Samsung presented a paper titled, “The World’s Most Energy Efficient MRAM Technology for Non-volatile RAM Applications” at the IEEE International Electron Devices Meeting (IEDM), a prominent micro- and nanoelectronics conference. The paper described nvRAM-oriented product technology based on Samsung’s 28nm and 14nm logic process nodes. As acknowledgment of the outstanding research and groundbreaking results it shared, the submission was selected as a highlight paper in the Memory category at IEDM. With this recognition, Samsung reached a new milestone. Specifically, the enhanced magnetic tunnel junction (MTJ) stack process technology dramatically lowered the Write Error Rate (WER). The MTJ has also advanced to a 14-nm FinFET process from the previous 28nm node, achieving 33% area scaling. This chip-scale sizing allows more chips to be produced from the same wafer, which results in more net dies. Additionally, it enables a 2.6x faster read cycle time1 and the packaging size has been reduced to 30mm2 at 16Mb, the industry’s smallest commercially available dimensions. This solution provides a near unlimited endurance of more than 1E142 cycles at -25°C. But perhaps the crowning achievement is the best-in-class energy efficiency with an active read and write power consumption of 14mW and 27mW, respectively at 54MB/s bandwidth. Samsung Electronics’ MRAM Innovation: Improved Switching Efficiency and MTJ Scaling The aforementioned 2022 paper reports two new major achievements for Samsung Electronics’ eMRAM: improved switching efficiency and MTJ scaling. Switching efficiency3 is the key metric for eMRAM performance. The graphs below display various measurements related to the WER from MTJ Stacks A to C4. As shown, Stack C suppressed delayed read meta-stable (DRM) WER up to two orders more than Stack A without negatively affecting retention. Additionally, repeated single-bit WER test results on an 8Mb array proved that WER distribution in the chip is 20% lower. Through the application of MTJ stack engineering, it was possible to validate a WER at the single-digit ppb5 level.
The second major achievement for eMRAM was improved MTJ scaling. In eMRAM architecture, reducing the size of MTJ is necessary to reduce write energy per bit since switching current is proportional to the MTJ bit area. However, due to the increase in cell resistance and variation during the MTJ scaling process, the endurance and read margins are known to degrade. In a display of innovation and ingenuity, Samsung’s research team has significantly improved6 the tunnel barrier process, reducing the resistance area by 25% and the short failure rate by a factor of 2.75. This has lowered the active write current of NVM-type eMRAM through reducing the size of the MTJ by 25% — in comparison to Flash-type eMRAM — and has also secured a sufficient manufacturing margin for MTJ size control. Expanding the eMRAM Portfolio: Targeting 8nm by 2026, 5nm by 2027 MTJ is formed between the back-end-of-line (BEOL) metal wiring processes without affecting the logic baseline, allowing the MRAM to scale-down to FinFET nodes with minimal MTJ process changes. Taking advantage of this, Samsung is upgrading from eMRAM 28nm technology to the 14nm FinFET process. This 14nm eMRAM is currently in development, in adherence to AEC-Q1007 Grade 1 — the global standard in reliability tests for automotive semiconductors. The aim is to complete development by 2024. At SFF 2023 in Europe, Samsung announced its vision to lead the next generation of automotive technology, disclosing its plan to develop the industry’s first 5nm eMRAM. In addition to the 14nm eMRAM by 2024, the company plans to further expand its eMRAM portfolio with 8nm by 2026 and 5nm by 2027. Compared to the 14nm process, the 8nm eMRAM is expected to deliver a 30% increase in density and 33% increase in speed. The next article in this series will examine the technical aspects of eMRAM, the memory technology poised to lead the electric and autonomous vehicle era.
1 Read Cycle Time: The time delay between the initiations of two successive memory read operations. 2 1E14: 100 trillion 3 Switching efficiency is calculated by dividing the energy barrier by the write bias. 4 “Stack A” refers to the existing POR stack process, and “Stack C” refers to the improved condition. 5 ppb: parts per billion, which equates to one write fail per one billion writes. 6 Reference: C. Park, et. al., “Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STTMRAM at 10 nm and Beyond,” VLSI Tech., pp. 185-186 (2018). 7 Automotive Electronic Council (AEC)-Q100: A stress test qualification for packaged integrated circuits used in automotive applications. Ambient operating temperature ranges are divided into four grades (0-3).

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