Samsung’s new HBM2 Aquabolt significantly extends the company’s leadership in driving the growth of the premium DRAM market. Moreover, Samsung will continue to offer leading-edge HBM2 solutions, to succeed its 1st-generation HBM2, HBM2 Flarebolt™, and its 2nd-generation, HBM2 Aquabolt, as it further expands the market over the next several years.
To achieve HBM2 Aquabolt’s unprecedented performance, Samsung has applied new technologies related to TSV design and thermal control. A single 8GB HBM2 package consists of eight 8Gb HBM2 dies, which are vertically interconnected using over 5,000 TSVs (Through Silicon Via’s) per die. While using so many TSVs can cause collateral clock skew, Samsung succeeded in minimizing the skew to a very modest level and significantly enhancing chip performance in the process.
In addition, Samsung increased the number of thermal bumps between the HBM2 dies, which enables stronger thermal control in each package. Also, the new HBM2 includes an additional protective layer at the bottom, which increases the package’s overall physical strength.
In accommodating the growing need for high-performance HBM2 DRAM, Samsung will supply HBM2 Aquabolt to its global IT customers at a stable pace, and continue to rapidly advance its memory technology in conjunction with leading OEMs throughout a wide array of fields including supercomputing, artificial intelligence, and graphics processing.
* Editor’s Note:
[HBM2 and GDDR5 data bandwidth calculation]
-An 8GB HBM2 package’s data bandwidth: 2.4Gbps per pin x 1024bit bus = 307.2GBps
Using four HBM2 packages in a system: 307.2GBps x 4 = 1228.8GBps = approximately 1.2TBps
-A 8Gb GDDR5 die’s data bandwidth: 8Gbps per pin x 32bit bus = 32GBps
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