The 300-mm TSV-bearing Silicon (Si) interposer wafer is manufactured by Samsung Foundry. There are two assembly processes depending on what format of Si interposer is being used: Chip on Substrate (CoS) or Chip on Wafer (CoW). In CoS, the Si interposer chip comes from a back-grinded and sawed Si interposer wafer. The chip is assembled on the package substrate. And then, the logic devices and HBM modules are mounted on top of it. In CoW, the logic devices and HBM modules are mounted on the back-grinded Si interposer wafer by following the wafer-level molding, grinding and sawing, and then the molded Si interposer die with devices is mounted on the package substrate. There is a major benefit with CoS: interim testing. Interim testing are for helping not to mount any faulted interposer or logic chips before HBM modules are mounted. There is a major benefit with CoW: larger. A larger Si interposer can be used for CoW. CoS helps to develop low-cost 2.5D packages and CoW helps to develop 2.5D packages with more HBM modules. Samsung Foundry has successfully qualified I-Cube™ which is available in a wide range of interposer sizes, HBM modules, and package sizes. Today, the 2.5D packages with 2x (1,600mm2) Si interposer integrating advanced logic chip and up to four HBM modules are fully qualified and available for production. Larger 2.5D packages with larger Si interposer integrating more than 4 HBM modules and 300nF/mm2 ISC™ (Integrated Stack Capacitor) are in development.