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Samsung Foundry’s Ambitions for a Comprehensive, Total Design Solution Explained at SAFE Forum 2022

This article is part of an in-depth series on the Foundry Business based on technology session presentations from Samsung’s SAFE Forum 2022. It shares expert perspectives on key SAFE ecosystem technologies and advancements.

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The more technology evolves, the more elusive a one-size-fits all approach becomes. Great ideas should never be constrained by the temptations of a catch-all solution. At the same time, however, companies need to be freed up to pursue their ambitions, so they need a foundry business they can depend on for the insight and the flexibility to accommodate whatever needs might arise, even for the most unique innovations. In a future where trail-blazing technologies are pushing boundaries in every direction – from automotive to mobile and IoT to HPC and AI – is it possible to build a foundry that can unify everything in one place? Samsung Foundry has been hard at work answering this question for years and, at October 2022’s SAFE Forum in San Jose, MJ Noh took to the stage to provide the latest on how the company is achieving just that. Responsible for the Foundry Design Service Team at Samsung Foundry headquarters in Korea, MJ’s talk covered how Samsung’s Advanced Design Platform is leveraging technologies like 2.5D and 3D solutions to provide customers with a turnkey service they know can accommodate the scale and specificity of tomorrow’s ideas. Building a Total Design Solution Under One Roof In previous forums, Samsung has focused on numerous branches of its Design Platform’s strong and wide-ranging capabilities in automobile, mobile, IoT and AI, including AEC-Q100 qualifications and ASIL standard readiness in automobile. HPC applications, meanwhile, have been growing particularly fast, and the foundry industry is looking to the dynamic modularity of chiplet architectures for answers. In all these areas, Samsung is remaining mindful of customer priorities when seeking a platform to work with: faster time to market through optimized production cycles and competitive Power, Performance and Area (PPA) capabilities, like DTCO (Design Technology Co-Optimization) and STCO (System Technology Co-Optimization). Finally, foundries need the ability to provide everything as part of a one-stop-shop of cutting edge design capabilities, with no third-party specialization required. Of course, providing all this is no simple matter. “Traditional chip design methods are faced with limitations caused by high cost and integration factors,” said MJ. “Even with silicon scaling, the number of transistors has continued to increase, pushing the limit of the maximum reticle size available, while the demand to integrate chips with various functions like these continues to rise. This causes a serious cost issue in both design and manufacturing.” As a result, MJ explained, scaling down the transistor size can never be enough to fulfill the growing complexity of applications, and this is where Samsung is taking the lead, thanks to constant progress in 2.5D and 3D chiplet solutions.
The Present and Future of 2.5 and 3D Thanks to cost effectiveness and versatility, 2.5D solutions are well placed to answer a variety of customer requirements, and Samsung stands ready to provide them to an excellent standard. “For the Power Integrity solution, we provide multi-plate Metal-Insulator-Metal (MIM) Cap and Integrated Stack Cap (ISC),” said MJ. “For IP solutions, High-bandwidth Die-to-Die IP is already silicon proven, and our HBM3 solution has been evaluated to run at up to 8Gbps.” The truly exciting stuff, however, MJ suggested, was in full 3D solutions. “The 3D approach allows higher manufacturing yield by splitting a big die into smaller ones,” said MJ. “We can reduce overall design cost by re-using Dies and IPs, while shorter interconnects mean faster performance and lower latency. It’s obvious that 3D stacking can achieve smaller form factors than when placing chiplets side-by-side.” After outlining a list of prominent 3D design challenges – including the cost of through-silicon vias (TSVs) and the higher thermal density that occurs with 3D vertical stacking – and their possible solutions, MJ continued by explaining how Samsung makes it all come together. “In order to minimize TSV design impact, we provide a number of TSV bundles,” MJ elaborated. “Regarding the Power Integrity Solution for 3D, we offer a variety of TSV schemes and optimal PPA-aware PDN, and to alleviate negative heat impact we have developed a Thermal Explorer. This provides thermal heat maps which help with the thermal-aware floorplan.”
Samsung’s 3DIC Journey Finally, MJ laid out Samsung Foundry’s overall 3DIC journey. By being involved in every stage of design, Samsung ensures it empathizes directly with customer needs and is fully in step with them in seeking solutions. “We have already developed SAINT-S, our SRAM stacking chip, and now we’re in the process of SAINT-L – a logic stack chip – development,” said MJ. “Soon we’ll be moving onto SAINT-D, which will handle DRAM stacking.” In the Big Die area, Samsung has developed a significant chip size of over 800 squared millimeters, while chiplets have been designed to integrate eight HBM3 chips on a huge interposer die, MJ explained. In the automotive safety and security field, meanwhile, several ADAS chips are already in mass production. “Our platform will help you make your ideas a reality and let you do so with high confidence,” MJ concluded. “I’d like to emphasize that our customers – as well as all nine Design Solution Partners – have full access to these platforms so that you can enjoy faster time to market, optimal performance and competitive cost.” Thanking customers and partners alike, MJ was confident of a bright future for the versatility and comprehensiveness of Samsung Foundry’s design environment. With more innovations to come, its work nurturing tomorrow’s life-changing technologies is far from over.

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