How Samsung’s 3D IC Cube is Reshaping the Foundry World

The world isn’t flat, and neither is the foundry industry. With its ever-changing performance needs and shifting landscape of competitors, it’s a multi-dimensional market that thrives on innovation. And yet despite major changes in the foundry world, chip designs have mostly stuck to their traditional flat structure. But is flat the best way to unleash today’s top performance? Samsung Foundry thinks otherwise, and has created 3D IC – a cube style solution that taps a new level of performance and goes beyond traditional scaling. As a multi-story infrastructure that moves us from flat chip to three dimensional cube, 3D IC is stacking memory and performance to make a “More than Moore” future a reality. Change Shapes, Change the Future

When Sangyun Kim, head of the Design Technology team at Samsung Foundry, stepped on stage for his keynote address at SAFE Forum 2022 in San Jose, he had a familiar message for the semiconductor industry. “Computing requirements are rapidly increasing,” he said – and scaling alone won’t be enough to keep up. His team’s job is to keep customers ahead of those rapid changes, which is the main thrust behind the formation of Cube technology. 3D IC Cubes stack chips into a cube like structure, combining the performance of multiple solutions into one cohesive unit. The result is stacked chips with faster communication between parts since information has a shorter space to travel when swapping messages compared to chip designs spread out over a one-dimensional pane. Space saving and cost cutting are also part of the package. But perhaps more important is its improved use of what’s called ‘heterogeneous integration’ – combining diverse and complementary chips into the same stack, thereby balancing one another’s strengths. “For example, the Top die can be 3GAA for high performance. The bottom die can be SF4 or even legacy node for cost saving, or IP reuse,” said Kim. By fitting more functionality into a small space, 3D IC solutions are extending Moore’s law of doubling capabilities in a way flat-chip thinkers wouldn’t have anticipated. But as expected, creating cube designs in a flat chip world comes with a new set of foundry challenges. The Challenges of Going 3D

3D IC solutions can only be achieved by using advanced foundry processes – and no discussion of Cube solutions would be completely without mentioning Through-Silicon Via (TSV). That’s the technology needed to make those wafer-to-wafer connections fast and efficient. TSV is used when building PDN for the top-die in a cube structure and has the critical job of signaling between top and bottom dies, creating the fast connections our customers rely on. Working with TSV creates numerous challenges to overcome. On top of those, we need a power delivery network to support the 3D IC stack through those TSVs and ubumps, all while meeting IR and EM requirements. Enabling TSV middle and TSV last in the same die is one solution we’ve found to provide a low resistivity option for power delivery. We’ve also enabled various types of TSV bundles to further reduce IR/EM risks for high performance applications. Going further, we minimized TSV and its keep-out zone penalties through stress simulations and silicon validation, then enabled the placement of certain devices into the keep-out zone to reduce the area penalty. Finally, we made our design flow TSV-aware by developing a macro friendly floorplan guide. Ubump-based bonding is another technology crucial to the 3D IC process. Samsung Foundry's ubump bonding technology has been tested across solutions and approved for mass production, enabling 3D ICs to be implemented in plethora devices at low cost. That allows customers to start by designing 3D ICs with these essential technologies and PDK, DK, IP, DM design infrastructure with minimum hurdles. A Question of Design But in the implementation of 3D IC solutions, there’s another key question that does not arise when dealing with flat chips: do we place function blocks on the top, or the bottom? To help customers answer that question, we’re developing a partitioning methodology for early-stage design in collaboration with our EDA partners. With these methodologies, every DOE can be analyzed for IR drop, while a designer is able to choose the best candidate for their use. The advantages here are massive: starting a 3D IC design with the right partition candidate can make turn-around-time faster than traditional methods. Despite all the challenges of working in a cube design, we’re still able to create a 3D design with only a few extra steps on top of the conventional 2D design flow. Most of that comes down to the placement of TSV, while aligning the ubump between the top and bottom dies also requires its own step. To ensure performance meets and exceeds standards, we put a strong focus on testing. We test the top and bottom dies separately first, then move on to testing for IEEE standard 1838 for 3D to ensure optimal die stacking. “Because this solution provides fundamental 3D test architecture for pre and post bond tests, it not only gives us a chance to make stacked die patterns more efficiently, but also provides us an assurance of quality,” Kim explained to the crowd at SAFE. If testing reveals unexpected defects, Samsung’s smart lane repair solutions can make the necessary changes to improve yields. Cutting Corners to Improve Sign-off Timing

Signoff challenges are a natural result of 3D IC construction – namely accounting for the possible lack of control dealing with varying sign-off corners. This is a side-effect of fabricating different technologies on each die. As a solution, Samsung has developed a new methodology called corner reduction, which uses dominant corners instead of full combinations in the timing sign-off. With IR/EM signoff, though, Samsung faced a different challenge entirely. Since the die power is supplied through a TSV that is not present in the existing 2D design, each die’s IR drop/EM can affect each other mutually – a challenge we’ve solved by analyzing the IR/EM of multiple dies at the same time. Partnering to Reshape Performance

Strong partnership is what drives semiconductor innovation, and many of these solutions were made possible directly as a result of working together with our EDA ECO partners. “Of course, overcoming new technical challenges is only a part of our work with EDA,” Kim reminded his audience. Along with four major EDAs, Samsung Foundry is successfully developing a 3D IC design flow from synthesis to sign-off – a work-in-progress that is coming to life with the help of SAFE EDA partners dedicated to creating better flow. No matter the technology, change is always driven by customer needs. The growing demand for multi die stacking has led to 2.5D and 3D chip solutions, opening new dimensions in performance and efficiency. Meeting those needs takes more than a one-size fits all approach. It requires us to move on from flat thinking and build in new dimensions. Just as we’ve moved on from the days of thinking the earth was flat, Samsung Foundry is always ready to reshape itself, its products, and the industry, as it works to bring customers the next level of innovation.