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3nm GAA MBCFET™: Unrivaled SRAM Design Flexibility

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On May 9 at ChipEx2023, Israel's largest semiconductor event, Samsung Foundry introduced their latest technologies and solutions under the theme “Foundry All Around”. One of the key topics at the event was 3nm Gate-All-Around (GAA) Multi-Bridge-Channel Field Effect Transistor (MBCFET™) technology and the Static Random Access Memory (SRAM) design flexibility it provides, and this article will take a closer look at the groundbreaking technology. The Development of 3nm GAA MBCFET™ Technology
GAA refers to the structure of a transistor. A transistor is a component of an electronic circuit that acts as an on/off switch, meaning that when a voltage is applied to the gate, current flows between the source and the drain, through the channel. In the optimization of transistor design, there are three key variables: Performance, Power and Area (PPA). Transistor manufacturers are in constant pursuit of higher performance, lower power requirements and smaller area for their products. As the size of transistors shrunk, their structure also evolved from Planar to Fin Field Effect Transistor (FinFET) and then to GAA in order to overcome limitations such as the short channel effect, which occurs when the distance between the source and drain is shortened, causing leakage current. At the forefront of the industry, Samsung Foundry started investigating GAA transistor structures in the early 2000s and started developing them in 2017 for application to the 3nm-class process, later beginning mass production using the world's first 3nm GAA MBCFET™ process in 2022. The Superior Design Flexibility of 3nm GAA MBCFET
As can be seen above, MBCFET provides superior design flexibility compared to FinFET. Transistors are designed to have different amounts of current flowing through them. In semiconductors that use many transistors, the amount of current must be regulated to turn transistors on and off at the required timing and control logic, which requires increasing or decreasing the width of the channel. In conventional FinFET structures, the height of the fin that the gate is wrapped around is not adjustable, so to increase the overall channel width, the number of fins is increased horizontally. But this method only enables the adjustment of the discontinuous channel width, because when the channel width of a gate-surrounded file is α, it can also only be decreased or increased by multiples of α. This is a serious limitation.  MBCFETs, on the other hand, are stacked on top of each other with the fins laid sideways, and the width of the nanosheets can be adjusted to provide more channel width options than FinFETs, which is a feature that can be useful for the entire design — with distinguished superiority in analog SRAM designs. MBCFETs offer these advantages because they have been designed to allow the channel width of the transistors to be fine-tuned independently in order to find an optimal balance between P-type metal-oxide-semiconductor transistors (PMOS) and N-type metal-oxide-semiconductor transistors (NMOS).
MBCFETs offer greater flexibility in SRAM cell design through tuning of the nanosheet width. The graphic on the left above shows a basic SRAM bitcell with six transistors. A Graphic Design System (GDS) view of this bitcell is shown in the middle image. In (a), in the GAA structure, the NMOS Pull-Down (PD) and Pass Gate (PG) have an identical channel width and the PMOS Pull-Up (PU) has a smaller channel width. (WPD = WPG > WPU ) In this case, it can be seen from the graph on the right that MBCFETs can secure a better margin than FinFETs. In (b), when the channel width is varied between the PD and PG, which are NMOS (WPD  > WPG  > WPU ), the margin is higher than that of (a). By adjusting the channel width to the role and characteristics of the transistor, the optimal balance is achieved, and the margin is secured. Since GAA SRAM bitcells require less power than FinFETs, and since the width of GAA can be adjusted independently for each transistor, the balance between PPA and the SRAM improves, significantly contributing to the design stability of the SRAM.

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