• Ansys, [John Lee, vice president and general manager of the Electronics, Semiconductor & Optics Business Unit at Ansys] “Together, Ansys and Samsung continue to deliver enabling technology for the most advanced designs, now at 3nm with GAA technology. The signoff fidelity of our Ansys multiphysics simulation platform is testament to our continued partnership with Samsung Foundry at the leading edge. Ansys remains committed to delivering the best design experience for our mutual advanced customers.” • Cadence, [Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence] “We congratulate Samsung on this 3nm GAA production release milestone. Cadence worked closely with Samsung Foundry to enable customers to achieve optimal power, performance, and area for this node using our digital solutions from library characterization to full digital flow implementation and signoff, all driven by our Cadence Cerebrus AI-based technology to maximize productivity. With our custom solutions, we collaborated with Samsung to enable and validate a full AMS flow to enhance productivity from circuit design and simulation through automated layout. We look forward to continuing this collaboration to achieve more tapeout successes.” • Siemens EDA, [Joe Sawicki, executive vice president for the IC-EDA segment of Siemens Digital Industries Software] “Siemens EDA is pleased to have collaborated with Samsung to help ensure that our existing software platforms also work on Samsung’s new 3-nanometer process node since the initial development phase. Our longtime partnership with Samsung through the SAFE program generates significant value for our mutual customers, by certification of Siemens industry-leading EDA tools at 3nm.” • Synopsys, [Shankar Krishnamoorthy, general manager and corporate staff for the Silicon Realization Group at Synopsys] “Through our long-standing, strategic collaboration with Samsung Foundry, we are enabling our solutions to support Samsung’s advanced processes, helping our mutual customers significantly accelerate their design cycles. Our support for Samsung’s 3nm process with GAA architecture continues expanding, now with our Synopsys Digital Design, Analog Design and IP products, enabling customers to deliver differentiated SoCs for key high-performance computing applications.”1 For more information on Design Technology Co-Optimization (DTCO), please see below links: Find the optimal for the best. Part 1 Find the optimal for the best. Part 2
Your subscription is not active yet!
An email with an activation link
has just been sent to your email address.
Please activate your subscription by clicking on
the activation link inside the email.
You have already registered, but before we can send you the
information about upcoming events, we need your confirmation.
If you missed our previous email, please use the button below to resend it.
To activate your subscription, please click on the link included in the email.
To proceed, please click on the "check" button located in the email section.Confirm