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Semiconductor R&D
Center

OPC Lab

Image processing, Computational geometry,
GPU, Deep Learning

Develops in-house computational lithography software and solutions to continuously
drive chip scaling.

Focus

OPC (optical proximity correction) is a resolution enhancement technology used to compensate for patterning process effects. It’s one of the critical steps in chip manufacturing. OPC group provides a complete in-house solution with GPU acceleration on image processing and computational geometry.

Teams

OPC team is comprised with three teams:

Software development team

Provides OPC software for different scanner systems and pathfinding on future technology nodes.

Product engineer team

Product development team to identify tape out issues and provide solutions with in-house tool.

SQA team

Monitor engineering process to ensure proper production software quality.

Location

Image of map indicating San Jose.

OPC Lab

3655 North 1st St. San Jose, CA 95134

MRAM Lab

3655 North 1st St. San Jose, CA 95134

Logic Path Finding Lab

3655 North 1st St. San Jose, CA 95134

MRAM Lab

MRAM (Magnetic Random Access Memory) Lab explores and invents novel materials and structures to realize spin-based logic and memory devices in near future.

Focus

Novel material exploration and design new device structure for energy efficient electrical manipulation of spins.

Teams

Theoretically calculates (ab-initio and micromagnetic simulations) to predict and understand properties and physics of spintronic materials and devices and their experimental demonstration to show proof of concept.

Location

Image of map indicating San Jose.

OPC Lab

3655 North 1st St. San Jose, CA 95134

MRAM Lab

3655 North 1st St. San Jose, CA 95134

Logic Path Finding Lab

3655 North 1st St. San Jose, CA 95134

Logic Path Finding Lab

Logic Path Finding Lab (LPL) identifies and evaluates future options for Logic Technology in collaboration with internal and external partners and consortia.

Focus

CMOS logic and SRAM scaling, new device architectures and embedded memories, new materials and processes to enable future logic technologies.

Teams

LPL is tasked with developing fundamental analyses to identify, develop, and help prove-out innovative technology elements for future (N+2 and N+3) Logic technologies. LPL collaborates with and guides research related to Logic technologies in consortia and US academia.

Location

Image of map indicating San Jose.

OPC Lab

3655 North 1st St. San Jose, CA 95134

MRAM Lab

3655 North 1st St. San Jose, CA 95134

Logic Path Finding Lab

3655 North 1st St. San Jose, CA 95134