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Advanced heterogeneous integration

New dimensions
to power a new era

Samsung Foundry's advanced heterogeneous integration technology empowers innovators to build the next generation of high-performance systems. Leveraging Samsung's expertise in advanced memory and packaging, chiplet and advanced packaging customers can seamlessly integrate compute dies and High Bandwidth Memory through advanced packaging and die-to-die interconnect—optimizing overall system performance and cost efficiency.

Advances in HPC/AI, 5G, autonomous vehicles, and immersive technologies are reshaping the way we live and connect. However, delivering the performance and functionality required to power these innovations on a single chip is becoming increasingly complex and less cost-effective.
Samsung Foundry's heterogeneous integration solutions overcome these challenges by bringing multiple chips, process nodes, and next-generation technologies together within one unified package – enhancing density, combining powerful functions, and optimizing overall cost efficiency.

Horizontal integration

Horizontal integration packaging utilizes parallel horizontal chip placement to enhance performance while effectively managing heat buildup. Samsung’s Through Silicon Via (TSV) and Backend-of-Line (BEOL) technologies provide the foundation for multiple chips to integrate their specialized functions – working together to deliver powerful, efficient solutions for modern devices.
Horizontal integration packaging is available in 2.5D Cube-S and 2.3D Cube-E/R configurations, each differentiated by interposer type.

2.5D Cube-S delivers high bandwidth and advanced performance with exceptional warpage control, even across large interposers.
2.5D Cube-S
  • 2.5D Cube-S delivers high bandwidth and advanced performance with exceptional warpage control, even across large interposers. It places logic chips and HBM dies horizontally on a silicon interposer, creating a high-bandwidth, low-latency data path for powerful computing performance.
    This enables excellent power integrity and high memory density, while significantly improving thermal efficiency for high-performance applications.

    • Supports Chip-on-Wafer (CoW) technology for developing 2.5D packages with higher HBM module count
    • 2.5D packages with 3.3x silicon interposer, integrating advanced logic and up to eight HBM modules, are fully qualified and available for production
    • Larger 2.5D packages with expanded silicon interposers are available, supporting more than eight HBM modules and 3,000nF/mm² or more ISC™ (Integrated Stack Capacitor)
    • Silicon interposer wafers are manufactured by Samsung Foundry
2.3D Cube-E features a silicon-embedded structure that combines the advantages of a fine-patterned silicon bridge, a TSV-less RDL interposer, and a large-area interposer enabled by FO-PLP (Fan-Out Panel-Level Packaging).
2.3D Cube-E
  • 2.3D Cube-E features a silicon-embedded structure that combines the advantages of a fine-patterned silicon bridge, a TSV-less RDL interposer, and a large-area interposer enabled by FO-PLP (Fan-Out Panel-Level Packaging).
    This architecture supports horizontal integration of diverse chip types—such as logic dies (CPU, GPU, NPU) and High Bandwidth Memory (HBM) dies—while providing improved cost efficiency for large, high-performance designs.

    • More cost-effective solution as size scales, compared to a full silicon implementation
    • Maintains fine line-and-space (L/S) routing benefits using silicon bridges embedded in an RDL interposer based on PLP technology, serving as interfaces between silicon dies.
    • Superior warpage control and power integrity for next-generation chiplet architectures
2.3D Cube-R features an organic RDL interposer architecture enabled by PLP or WLP technologies, delivering high performance with significant cost and size advantages.
2.3D Cube-R
  • 2.3D Cube-R features an organic RDL interposer architecture enabled by PLP or WLP technologies, delivering high performance with relatively low cost and size advantages.
    This structure enhances signal integrity and bump joint reliability while supporting multi-chip integration and higher I/O counts. It also improves electrical performance through thicker Cu RDL and helps minimize warpage by leveraging standard flip-chip assembly.

    • Provides a cost-effective alternative to a Si-Bridge solution.
    • Enables shorter product development and mass production time, through a simplified assembly process flow
    • Samsung Foundry is developing a 2.3D RDL interposer technology with a line and a space width of 2/2㎛.

Vertical integration

Vertical integration packaging further boosts performance by shortening interconnect wire lengths through vertical stacking, enabling ultra-high interconnect density with lower parasitics while saving significant on-chip area. It also reduces yield risk associated with large monolithic dies through advanced 3D integration – delivering higher system performance at lower cost while maintaining high bandwidth and power efficiency.

3D Cube-T is a leap forward in advanced packaging, stacking logic dies along the Z-axis and enabling precise die alignment using TSV (Through Silicon Via) technology, followed by robust interconnects through thermal-compression bonding.
3D Cube-T
  • 3D Cube-T is a leap forward in advanced packaging, stacking logic dies along the Z-axis and enabling precise die alignment using TSV (Through Silicon Via) technology, followed by robust interconnects through thermal-compression bonding.
    Samsung’s continued innovation in Chip-on-Wafer (CoW) technology delivers higher speed and performance, enabling greater chip density per stack while maintaining high throughput and power efficiency--making it an ideal 3D packaging solution for next-generation high-performance computing applications.

    • Enables higher density, scalability, lower latency, and higher bandwidth through 3D packaging
    • Proven 3D packaging with high-bandwidth memory (HBM) and CMOS image sensor (CIS)
    • Ready for mass production using micro-bump CoW and TSV technologies for low-power 3D IC applications
3D Cube-H enhances chip-to-chip interconnection between chips by stacking logic dies along the Z-axis and enabling precise die alignment using TSV (Through Silicon Via) technology, followed by robust interconnection through Hybrid Cu-Cu connections.
3D Cube-H
  • 3D Cube-H enhances chip-to-chip interconnection between chips by stacking logic dies along the Z-axis and enabling precise die alignment using TSV (Through Silicon Via) technology, followed by robust interconnection through Hybrid Cu-Cu connections. It offers significant advantages in layout flexibility compared to conventional chip stacking technologies, making it well suited for highly integrated designs. Samsung Foundry is currently developing ultra-fine-pitch Cu-Cu interconnects with dimensions below 4μm to support high-performance computing workloads.

    • Delivers highest transistor density and shortest vertical signal paths
    • Reduces form factor by eliminating bump bonds and other packaging components
    • Bumpless hybrid Die-to-Wafer (D2W) technology under development

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