Skip to content
Tech Blog

Find the optimal for the best. Part 2

- GAA MBCFET™ PPA optimization through DTCO of Samsung Foundry

  • mail
Samsung Foundry officially presented a paper “3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for Succeeding PPA by Technology GAA” at the 2022 IEEE CICC(Custom Integrated Circuits Conference) on April 26. The purpose of this article is to help readers have better understanding on DTCO activities that could maximize the PPA advantages on 3nm GAA MBCFET™. 1. MBCFET™ PPA optimization: DTCO In part 1, DTCO (Design-Technology Co-Optimization) was introduced as overall activities for PPA (power, performance, and area) optimization. The previous version was mainly highlighted various advantages from PPA’s perspective. Not only these features, but DTCO also aims to maximize the ‘PPA Wise’ through optimization. In part 2, Samsung would like to share general DTCO before diving into DTCO of MBCFET™. 2. Optimal recipe Maker, DTCO DTCO is an overall process to find an optimal point considering both process and design in order to provide customers with the best combination of Samsung’s technological power. Let’s go into details regarding the activities performed in terms of power, performance, and area below.

A. Optimization for small area First, let’s talk about DTCO from the standpoint of area. Simply, it is an activity focusing on reducing area. Also, it finds a solution for reducing area while minimizing power overflow or performance decrease. Please see the below Fig [1], Fig[2], Fig[3].

Fig. [1] Circuit diagram of inverter comprising two transistors
Fig. [1] Circuit diagram of inverter comprising two transistors
Fig. [1] Circuit diagram of inverter comprising two transistors
Fig. [2] FinFET-structure transistor built according to the circuit diagram
Fig. [2] FinFET-structure transistor built according to the circuit diagram
Fig. [2] FinFET-structure transistor built according to the circuit diagram
Fig. [3] FinFET-structure transistor layout ( Top view )
Fig. [3] FinFET-structure transistor layout ( Top view )
Fig. [3] FinFET-structure transistor layout ( Top view )

The easiest way to reduce area would be to minimize the size of all elements from 1 to 8 in Fig. [3]. However, each of these elements require a minimum area from their purposes and process capacities, and these changes alter the factors affecting performance (resistance and capacitance). So, DTCO performs activities to determine the optimal size and distance by considering both process and design. In other words, DTCO is a process to secure a minimized area through optimization. B. Optimization for low power As mentioned in the previous article, power is the multiplication of voltage and current. Power is closely related to performance. Good performance refers to a state where the circuit operating speed can be improved by letting a large amount of current flow. However, performance is in a trade-off relationship with power. A large amount of voltage is required to let a large amount of current flow or to control the current more effectively. Just like how opening an aqueduct requires a larger amount of force than a water faucet. But, we need a method to lower the amount of power consumed while keeping the same performance level. The faucet in (a) of Fig. [4] seems it would require an extremely large amount of force to open and close it. Then, what do we need to open and close this faucet using a small amount of force? We need an item that can help us, such as the handles and lever in (b) of Fig. [4]. This is same in chip design. For a chip to provide appropriate functions at low voltage with each transistor operating successfully, it requires assist circuit. However, as even faucet handles have varying shapes and materials, these additional elements also have different PPA-wise strengths. Through DTCO, we are finding and applying assistive circuit to ensure the optimal PPA. This is a process to find the optimized lowest power. Fig. [5]

Fig. [4] To open a faucet (A), an assistive device, such as the handles in (B), is required.
Fig. [4] To open a faucet (A), an assistive device, such as the handles in (B), is required.
Fig. [4] To open a faucet (A), an assistive device, such as the handles in (B), is required.
Fig. [5] PPA analysis by assistive circuit
Fig. [5] PPA analysis by assistive circuit
Fig. [5] PPA analysis by assistive circuit

C. Optimization for high performance Lastly, let’s talk about DTCO in terms of performance. To ensure high performance, it is necessary to minimize the factors that occur unintentionally in the process of chip design and impede performance (resistance and capacitance, etc.) through DTCO. Let’s take an example of resistance. Resistance increases when the path is longer and narrower, and this leads to performance deterioration. Just like how it takes longer for the same amount of water to flow through an aqueduct if the aqueduct is narrower or longer. Fig[6]

Fig. [6] Comparing resistance to aqueduct (resistance smallest in (b) and largest in (c))
Fig. [6] Comparing resistance to aqueduct (resistance smallest in (b) and largest in (c))
Fig. [6] Comparing resistance to aqueduct (resistance smallest in (b) and largest in (c))

Fig. [7] shows the path of current flowing, that is, wiring. As in the example above, when current flows from A to B, reducing the path is to reduce resistance, and this can lead to performance improvement. In A of Fig. [7], the blue layer (Layer 1) and green layer (Layer 2) can provide paths only in the longitudinal and transverse directions respectively. This is not logical for the shortest path setting. In (b), however, the blue layer (Layer 1) can provide paths in both longitudinal and transverse directions. Therefore, resistance can be reduced using the short path.

Fig. [7] A : Each layer providing uni-directional path, B : Bi-directional path provided
Fig. [7] A : Each layer providing uni-directional path, B : Bi-directional path provided
Fig. [7] (a) Each layer providing uni-directional path (b) Bi-directional path provided

The importance of DTCO activity, as such, is increasing as transistors are becoming smaller. For the small and sensitive transistors, even a small change can have a significant impact. This is the reason the importance of DTCO in MBCFET is being stressed. Now, let’s go into the DTCO-wise strengths of MBCFET.

3. MBCFET™, Samsung’s GAA optimized to optimization To get straight to the point, MBCFET has a strength to provide a greater variety of potentials for DTCO. This means that the factors limiting DTCO activities in transistors have been reduced. Let’s go over the factors one by one.

A. Reducing performance loss caused by change With the existing transistors, partial performance deterioration was inevitable when the channel width was increased or operating voltage was decreased. This is because, as explained in the previous posting, these are in a trade-off relationship. For MBCFET, we increased the field of DTCO activities by lowering performance deterioration.

i. Minimizing performance loss caused by channel width increase Increasing channel width for the purpose of performance improvement can result in unintentional performance loss. This means that the effect of channel width increase is not entirely led to performance improvement. It is caused by the factors impeding performance (resistance and capacitance, etc.) that occur among the structural elements. In a nutshell, this is an unavoidable phenomenon that follows a structural change. As the scale of this phenomenon depends on the structure, a difference in the structure leads to a difference in the size of performance loss. FinFET and MBCFET have a large structural difference. That being the case, there is also a difference in the size of performance loss. As mentioned earlier, FinFET requires one more fin to increase the channel width. So, compared to MBCFET, it involves a greater structural change. In Fig. [8], you can see that, compared to increasing the width of an aqueduct, building another aqueduct involves the formation of an unnecessary structure (the yellow area), although the width of the two aqueducts is the same. In FinFET, a greater performance loss is caused by the structural change. With MBCFET, this limitation is overcome because it does not require an additional structure like a fin to adjust the width.

Fig. [8] Two types of aqueduct with the same width
Fig. [8] Two types of aqueduct with the same width
Fig. [8] Two types of aqueduct with the same width

ii. Minimizing performance deterioration caused by low power The goal to lower operating voltage for low power consumption was explained in the previous posting. It was also explained through an example of the sluice and faucet that low operating voltage also reduces the amount of current flowing. However, as MBCFET has a wider channel than FinFET, the amount of current flowing in MBCFET is larger even at low operating voltage. This is like how a far more amount of water comes out from a faucet even if opened by a little bit when the water pipe itself is wider. For MBCFET, the performance deterioration has been kept to a minimum by letting a large amount of current flow at low operating voltage.

B. Customized transistor - Flexibility (design convenience) Reducing performance loss caused by change is not all. As explained in the previous posting, continuous channel width adjustment is possible with MBCFET™. In addition to providing a channel width that better complies with the level required by design, channel width adjustment for optimization has been facilitated.

Based on the merit above, DTCO has secured far greater potentials. As you can see in Fig. [9], MBCFET™, unlike FinFET, can find and move to the PPA fields outside the simple scope of its activities through DTCO. Also, as in Fig. [10], a wide range of channel widths and improved performances from NS1 to NS4 are available. Moreover, through reduction of operating voltage, power consumption can be further decreased.
Fig. [9] PPA levels by design purpose (HD (high density)/HP (high performance))
Fig. [9] PPA levels by design purpose (HD (high density)/HP (high performance))
Fig. [9] PPA levels by design purpose (HD (high density)/HP (high performance))
Fig. [10] GAA that provides various channel widths and performance options
Fig. [10] GAA that provides various channel widths and performance options
Fig. [10] GAA that provides various channel widths and performance options
Samsung’s MBCFET™ has opened up a new possibility for DTCO and is conducting it to help our customers experience the PPA advantages of MBCFET™ as much as possible. This advancement to MBCFET™ will provide the best process to customers and it has also enabled Samsung to provide greater support in its process. At Samsung Foundry, we have been and will continue providing not only the outstanding process, but also design-related supports to let customers produce the optimal outcomes.